WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 159

• Manufacturer Part Number: WG82577LM S LGWR
• Manufacturer: Intel

Specifications of WG82577LM S LGWR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
Figure 19.
10.2.1.3.20 Receive Address Low - RAL (0x05400 + 8*n (n=0…6); RW)
10.2.1.3.21 Receive Address High - RAH (0x05404 + 8*n (n=0…6); RW)
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
Multicast Table Array Algorithm
While “n” is the exact unicast/multicast address entry and it is equals to 0,1,…6.
While “n” is the exact unicast/multicast address entry and it is equals to 0,1,…6.
31:0
00b
01b
10b
11b
Bits
RW
Type
Multicast Offset
MO1:0]
X
Reset
Receive Address Low (RAL). The lower 32 bits of the 48-bit Ethernet address n
(n=0, 1…6). RAL 0 is loaded from words 0 and 1 in the NVM.
47:40 39:32 31:24 23:16
DA[47:38] = Byte 6 bits 7:0, Byte 5 bits 7:6
DA[46:37] = Byte 6 bits 6:0, Byte 5 bits 7:5
DA[45:36] = Byte 6 bits 5:0, Byte 5 bits 7:4
DA[43:34] = Byte 6 bits 3:0, Byte 5 bits 7:2
Bits Directed to the Multicast Table Array
pointer[9:5]
word
Destination Address
bit
pointer[4:0]
Description
Multicast Table Array
(1024 bit vector)
32 x 32
15:8
...
...
?
7:0
152