WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 131

• Manufacturer Part Number: WG82577LM S LGWR
• Manufacturer: Intel

Specifications of WG82577LM S LGWR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
10.2.1.1.3
10.2.1.1.4
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
Strapping Option Register - STRAP (0x0000C; RO)
This register reflects the values of the soft strapping options fetched from the NVM
descriptor in the Intel
the MAC following LAN_RST# or global reset (PCI reset assertion).
Extended Device Control Register - CTRL_EXT (0x00018; RW)
0
5:1
10:6
15:11
16
23:17
24
31:25
11:0
12
14:13
15
18:16
19
20
24:21
25
26
27
Bit(s)
Bits
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW/V
RW
RW/SN
RW/SN
RW
RW
RW
Type
Type
00b
0b
000b
0b
1b
0000b
0b
0b
0b
1b
0x0
0x0
0x0
0b
0x0
0b
0x0
0x0
1b
®
Reset
Reset
5 Series Express Chipset space. These signals are sampled by
Reserved.
Reserved.
Reserved.
Speed Select Bypass (SPD_BYPS). When set to 1, all speed detection
mechanisms are bypassed, and the device is immediately set to the speed
indicated by CTRL.SPEED. This provides a method for software to have full
control of the speed settings of the device when the change takes place by
overriding hardware clock switching circuitry.
Reserved.
Dynamic Clock Gating (DynCK). When set, this bit enables dynamic clock
gating of the DMA and MAC units. Refer to the description of the
DynWakeCK in this register. This bit is loaded from NVM word 0x13.
PHY Power Down Enable (PHYPDEN). When set, this bit enables the 82577
to enter a low-power state when the MAC is at the DMoff / D3 or Dr with
no WoL. This bit is loaded from word 0x13 in the NVM.
Reserved.
DMA Clock Control (DMACKCTL). Controls the DMA clock source in non-
GbE mode (10/100 and no Link). In GbE mode, the DMA clock source is
always GLCI PLL divided by two. In normal operation, this bit should be in
the default state in which the DMA clock source in non-GbE is mosc_clk.
In test mode the DMACKCTL and PLLGateDis should be set to 1b and
CLK_CNT_1_4 in the NVM should not be set. In this mode, the DMA clock
source is GLCI PLL divided by two.
Disable Static GLCI PLL Gating (PLLGateDis). By default the PLL is
functional only when the GLCI link is required, and inactive when it is not
required (at non-GbE mode if LCI is available). When set to 1b the GLCI
PLL is always active.
Interrupt Acknowledge Auto-Mask Enable (IAME). When this bit is set, a
read or write to the ICR register has the side effect of writing the value in
the IAM register to the IMC register. When this bit is 0b, this feature is
disabled.
Reserved.
LAN NVM Size (NVMS). LAN NVM space size is indicated in multiples of 4
KB. LAN NVM size might very from 4 KB to 128 KB (a zero value means 4
KB).
Reserved.
Reserved.
MAC SMBus address enable (LCSMBADDEN).
MAC SMBus address (LCSMBADD).
PHY SMBus address enable (LCDSMBADDEN).
PHY SMBus address (LCDSMBADD).
Description
Description
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