WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 68

• Manufacturer Part Number: WG82577LM S LGWR
• Manufacturer: Intel

Specifications of WG82577LM S LGWR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 29.
Table 30.
61
Management Interface (MI) Register - Address 21
PHY Configuration Register - Address 22
15:4
3
2:0
15
14
13:12
11:10
9:8
7
6
5
4:0
Bits
Bits
Reserved
Energy Detect
Power Down Enable
Reserved
CRS Transmit Enable
Reserved
Transmit FIFO Depth
(1000BASE-T)
Automatic Speed
Downshift Mode
Reserved
Alternate Next Page
Group MDIO Mode
Enable
Transmit Clock Enable
Reserved
Field
Field
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
X
Default
0b
1b
01b
GX
0b
0b
0b
0x0
Default
Reserved
1b = Enables energy detect power down.
0b = Disables energy detect power down.
Reserved
82577 GbE PHY—Programmer’s Visible State
1b = Enables Carrier Sense Indication (CRS)
on transmit in half-duplex mode.
0b = Disables CRS on transmit.
Reserved
00b = +/-8.
01b = +/-16.
10b = +/-24.
11b = +/-32.
If automatic downshift is enabled and the
PHY fails to auto-negotiate at 1000BASE-T,
the PHY falls back to attempt connection at
100BASE-TX and, subsequently, 10BASE-T.
This cycle repeats. If the link is broken at any
speed, the PHY restarts this process by re-
attempting connection at the highest possible
speed (1000BASE-T).
00b = Automatic speed downshift disabled.
01b = 10BASE-T downshift enabled.
10b = 100BASE-TX downshift enabled.
11b = 100BASE-TX and 10BASE-T enabled.
Reserved
1b = Enables manual control of 1000BASE-T
next pages only.
0b = Normal operation of 1000BASE-T next
page exchange.
1b = Enables group MDIO mode.
0b = Disables group MDIO mode.
When this bit is set, the transmit test clock is
available on pin TX_TCLK.
1b = Enables output of mixer clock (transmit
clock in 1000BASE-T).
0b = Disables output.
Reserved
Description
Description