WG82577LM S LGWR Intel, WG82577LM S LGWR Datasheet - Page 142

• Manufacturer Part Number: WG82577LM S LGWR
• Manufacturer: Intel

Specifications of WG82577LM S LGWR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.2.1.2.2
135
This register contains all interrupt conditions for the MAC. Each time an interrupt
causing event occurs, the corresponding interrupt bit is set in this register. An interrupt
is generated each time one of the bits in this register is set, and the corresponding
interrupt is enabled via the Interrupt Mask Set/Read register (see
Each time an interrupt causing event occurs, all timers of delayed interrupts are cleared
and their cause event is set in the ICR.
Writing a 1b to any bit in the register also clears that bit. Writing a 0b to any bit has no
effect on that bit. The INT_ASSERTED bit is a special case. Writing a 1b or 0b to this bit
has no affect. It is cleared only when all interrupt sources are cleared.
Interrupt Throttling Register - ITR (0x000C4; RW)
Software can use this register to pace (or even out) the delivery of interrupts to the
host CPU. This register provides a guaranteed inter-interrupt delay between interrupts
asserted by the network controller, regardless of network traffic conditions. To
independently validate configuration settings, software can use the following algorithm
to convert the inter-interrupt interval value to the common 'interrupts/sec'
performance metric:
Interrupts/sec = (256 x 10
For example, if the interval is programmed to 500d, the network controller guarantees
the CPU is not interrupted by the network controller for 128 ms from the last interrupt.
16
17
21:18
22
30:23
31
15:0
31:16
• Read ICR register is affected differently in the following cases:
Bit
Bit
— Case 1 - Interrupt Mask register equals 0x0000 (mask all) - ICR content is
— Case 2 - Interrupt was asserted (ICR.INT_ASSERTED=1) - ICR content is
— Case 3 - Interrupt was not asserted (ICR.INT_ASSERTED=0) - Read has no
cleared.
cleared and auto mask is active, meaning, the IAM register is written to the
IMC register.
side affect.
RWC/CR/V
RWC/CR/V
RWC/CR/V
RWC/CR/V
RO
RWC/CR/V
RW
RO
Type
Type
82577 GbE PHY—Intel
0x0
0x0
0b
0b
0x0
0b
0x0
0b
Reset
Reset
-9
Small Receive Packet Detected (SRPD). Indicates that a packet size
< RSRPD.SIZE register has been detected and transferred to host
memory. The interrupt is only asserted if RSRPD.SIZE register has a non-
zero value.
Receive ACK Frame Detected (ACK). Indicates that an ACK frame has been
received and the timer in RAID.ACK_DELAY has expired.
Reserved.
ECC Error (ECCER). Indicates an uncorrectable EEC error occurred.
Reserved. Reads as 0b.
Interrupt Asserted (INT_ASSERTED). This bit is set when the LAN port has
a pending interrupt. If the Interrupt is enabled in the PCI configuration
space, an interrupt is asserted.
sec x interval)
INTERVAL. Minimum inter-interrupt interval. The interval is specified in
256 ns units. Zero disables interrupt throttling logic.
Reserved. Should be written with 0b to ensure future compatibility.
®
5 Series Express Chipset MAC Programming Interface
-1
Description
Description
Section
10.2.1.3.5).