PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 90
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PSB3186FV1.4
Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet
1.PSB3186FV1.4.pdf
(207 pages)
Specifications of PSB3186FV1.4
Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
Details
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• As a slave device the transceiver part of the ISAC-SX TE is programmed and
• For data exchange between two microcontroller systems attached to two different
3.7.3.1
The MONITOR channel operates on an asynchronous basis. While data transfers on the
bus take place synchronized to frame sync, the flow of data is controlled by a handshake
procedure using the MONITOR Channel Receive (MR) and MONITOR Channel
Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit is
activated. This data will be transmitted once per 8-kHz frame until the transfer is
acknowledged via the MR bit.
The MONITOR channel protocol is described in the following section and
illustrates this. The relevant control and status bits for transmission and reception are
listed in
Table 11
Table 12
Data Sheet
Control/
Status Bit
Control
Status
Control/
Status Bit
Control
Status
controlled from a master device on IOM-2 (e.g. ISAR34 PSB 7115). This is used in
applications where no microcontroller is connected directly to the ISAC-SX TE in order
to simplify host interface connection. The HDLC controlling is processed by the master
device therefore the HDLC data is transferred via IOM-2 interface directly to the
master device.
devices on one IOM-2 backplane. Use of the MONITOR channel avoids the necessity
of a dedicated serial communication path between the two systems. This simplifies the
system design of terminal equipment.
Table 11
Handshake Procedure
Register
MOCR
MOSR
MSTA
Register
MOCR
MOSR
Transmit Direction
Receive Direction
and
Table
Bit
MXC
MIE
MDA
MAB
MAC
Bit
MRC
MRE
MDR
MER
12.
Function
MX Bit Control
Transmit Interrupt Enable
Data Acknowledged
Data Abort
Transmission Active
Function
MR Bit Control
Receive Interrupt Enable
Data Received
End of Reception
90
Description of Functional Blocks
PSB 3186
PSF 3186
2000-08-23
Figure 47
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