PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 166

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

4.3.8
Value after reset: 08
IOM_CR
SPU ... Software Power Up
0: The DU line is normally used for transmitting data
1: Setting this bit to ’1’ will pull the DU line to low. This will enforce connected layer 1
devices to deliver IOM-clocking.
After a subsequent ISTA.CIC-interrupt (C/I-code change) and reception of the C/I-code
”PU” (Power Up indication in TE-mode) the microcontroller writes an AR or TIM
command as C/I-code in the CIX0-register, resets the SPU bit and waits for the following
CIC-interrupt.
For general information please refer to
CI_CS ... C/I Channel Selection
The channel selection for D-channel and C/I-channel is done in the channel select bits
CH2-0 of register TR_CR (for the transceiver) and DCI_CR (for the D-channel controller
and C/I-channel controller).
0: A write access to CS2-0 has effect on the configuration of D- and C/I-channel,
whereas a read access delivers the D-channel configuration only.
1: A write access to CS2-0 has effect on the configuration of the C/I-channel only,
whereas a read access delivers the C/I-channel configuration only.
TIC_DIS ... TIC Bus Disable
0: The last octet of IOM channel 2 (12th timeslot) is used as TIC bus.
1: The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used
as every time slot.
EN_BCL ... Enable Bit Clock BCL
0: The BCL clock is disabled
1: The BCL clock is enabled.
Data Sheet
7
IOM_CR - Control Register IOM Data
SPU
H
0
CI_CS TIC_
DIS
Chapter
166
EN_
BCL
3.7.6.
CLKM DIS_
Detailed Register Description
OD
0
DIS_
IOM
RD/WR (57)
PSB 3186
PSF 3186
2000-08-23