PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 100

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several
consecutive codes are detected, only the first and the last code is obtained at the first
and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
Figure 52
3.7.5
D-channel access control is defined to guarantee all connected TEs and HDLC
controllers a fair chance to transmit data in the D-channel. Collisions are possible
• on the IOM-2 interface if there is more than one HDLC controller connected or
• on the S-interface when there is more than one terminal connected in a point to
Both arbitration mechanisms are implemented in the ISAC-SX TE and will be described
in the following two chapters.
3.7.5.1
The TIC bus is imlemented to organize the access to the layer-1 functions provided in
the ISAC-SX TE (C/I-channel) and to the D-channel from up to 7 external communication
controllers
Data Sheet
multipoint configuration (NT
(Figure
D-Channel Access Control
TIC Bus D-Channel Access Control
CIC Interrupt Structure
TRAN
MASK
WOV
MOS
ICD
CIC
ST
Interrupt
53).
TRAN
ISTA
WOV
MOS
ICD
CIC
ST
TE1 … TE8).
100
CI1E
CIX1
Description of Functional Blocks
CIC0
CIC1
CIR0
PSB 3186
PSF 3186
2000-08-23