PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 153
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PSB3186FV1.4
Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet
1.PSB3186FV1.4.pdf
(207 pages)
Specifications of PSB3186FV1.4
Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
Details
- Current page: 153 of 207
- Download datasheet (3Mb)
1: The phase deviation is 2 S-bits minus 9 oscillator periods plus analog delay plus
For general information please refer to
RLP ... Remote Line Loop
0: Remote Line Loop open
1: Remote Line Loop closed
For general information please refer to
4.2.4
Value after reset: 00
TR_STA
RINF ... Receiver INFO
00: Received INFO 0
01: Received any signal except INFO 1 - 4
10: Received INFO 2
11: Received INFO 4
SLIP ... SLIP Detected
A ’1’ in this bit position indicates that a SLIP is detected in the receive or transmit path.
ICV ... Illegal Code Violation
0: No illegal code violation is detected
1: llegal code violation (ANSI T1.605) in data stream is detected
FSYN ... Frame Synchronization State
0: The S/T receiver is not synchronized
1: The S/T receiver has synchronized to the framing bit F
LD ... Level Detection
0: No receive signal has been detected on the line.
1: Any receive signal has been detected on the line.
Data Sheet
delay of the external circuitry.
delay of the external circuitry.
7
TR_STA - Transceiver Status Register
RINF
H
SLIP
ICV
Chapter
Chapter
153
0
3.3.7.
3.3.10.
FSYN
Detailed Register Description
0
0
LD
PSB 3186
PSF 3186
2000-08-23
RD (33)
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