PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 86
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PSB3186FV1.4
Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet
1.PSB3186FV1.4.pdf
(207 pages)
Specifications of PSB3186FV1.4
Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
Details
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3.7.2
For timeslot oriented standard devices connected to the IOM-2 interface the ISAC-SX
TE provides an independent data strobe signal SDS. Instead of a data strobe signal a
strobed IOM-2 bit clock can be provided on pin SDS.
3.7.2.1
The strobe signal can be generated with every 8-kHz frame and is controlled by the
register SDS_CR. By programming the TSS bits and three enable bits (ENS_TSS,
ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM-2 timeslots TS,
TS+1 and TS+3 and any combination of them.
The data strobe for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data
strobe for TS+3 is always 2 bits long (bit7, bit6).
Figure 44
SDS is active during channel B2 on IOM-2 whereas in the second example during IC2
and MON1. The third example shows a strobe signal for 2B+D channels which can be
used e.g. for an IDSL (144kbit/s) transmission.
Data Sheet
shows three examples for the generation of a strobe signal. In example 1 the
Serial Data Strobe Signal and Strobed Data Clock
Serial Data Strobe Signal
86
Description of Functional Blocks
PSB 3186
PSF 3186
2000-08-23
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