PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 120

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

PSB 3186
PSF 3186
Description of Functional Blocks
With a selected block size of 16 bytes an XPR interrupt indicates when a transmit FIFO
space of at least 16 bytes is available to accept further data, i.e. there are still a maximum
of 48 bytes (64 bytes - 16 bytes) to be transmitted. With a 32 bytes block size the XPR
is initiated when a transmit FIFO space of at least 32 bytes is available to accept further
data, i.e. there are still a maximum of 32 bytes (64 bytes - 32 bytes) to be transmitted.
The maximum reaction time for the smaller block size is 50 % higher with the trade-off
of a doubled interrupt load. With a selected block size an XPR always indicates the
available space in the XFIFOD, so any number of bytes smaller than the selected XFBS
may be stored in the FIFO during one “write block“ access cycle.
Similar to RFBS for the receive FIFO, a new setting of XFBS takes effect after the next
XTF, XME or XRES command. XRES resets the XFIFOD.
The XFIFOD can hold any number of frames fitting in the 64 bytes.
Possible Error Conditions during Transmission of Frames
If the transmitter sees an empty FIFO, i.e. if the microcontroller doesn’t react fast enough
to an XPR interrupt, an XDU (transmit data underrun) interrupt will be generated. If the
HDLC channel becomes unavailable during transmission the transmitter tries to repeat
the current frame as specified in the LAPD protocol. This is impossible after the first data
block has been sent (16 or 32 bytes), in this case an XMR transmit message repeat
interrupt is set and the microcontroller has to send the whole frame again.
Both XMR and XDU interrupts cause a reset of the XFIFOD. The XFIFOD is locked while
an XMR or XDU interrupt is pending, i.d. all write actions of the microcontroller will be
ignored as long as the microcontroller hasn’t read the ISTAD register with the set XDU,
XMR interrupts.
If the microcontroller writes more data than allowed (block size), then the data in the
XFIFOD will be corrupted and the STARD.XDOV bit is set. If this happens, the
microcontroller has to abort the transmission by CMDRD.XRES and start new.
The general procedures for a data transmission sequence are outlined in the flow
diagram in
Figure
63.
Data Sheet
120
2000-08-23