PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 161
PSB3186FV1.4
Manufacturer Part Number
PSB3186FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet
1.PSB3186FV1.4.pdf
(207 pages)
Specifications of PSB3186FV1.4
Control Type
HDLC
Data Rate
192 Kbps
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Package / Case
MQFP-64
Lead Free Status / Rohs Status
Details
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4.3.4
Value after reset: F8
TR_CR
Read and write access to this register is only possible if IOM_CR.CI_CS = 0.
EN_D ... Enable Transceiver D-Channel Data
EN_B2R ... Enable Transceiver B2 Receive Data
EN_B1R ... Enable Transceiver B1 Receive Data
EN_B2X ... Enable Transceiver B2 Transmit Data
EN_B1X ... Enable Transceiver B1 Transmit Data
This register is used to individually enable/disable the D-channel (both RX and TX
direction) and the receive/transmit paths for the B-channel of the S-transceiver.
0: The corresponding data path to the transceiver is disabled.
1: The corresponding data path to the transceiver is enabled.
CS2-0 ... Channel Select for Transceiver D-channel
This register is used to select one of eight IOM channels to which the transceiver D-
channel data is related to.
Note: It should be noted that writing TR_CR.CS2-0 will also write to TRC_CR.CS2-0 and
Data Sheet
therefore modify the channel selection for the transceiver
C/I0 data.
7
TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0)
EN_
D
EN_
B2R
H
EN_
B1R
EN_
B2X
161
EN_
B1X
Detailed Register Description
CS2-0
0
RD/WR (50)
PSB 3186
PSF 3186
2000-08-23
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