PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 10

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

List of Figures
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Data Sheet
Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 80
Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 81
Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 84
Examples for the Synchronous Transfer Interrupt Control with
one enabled STIxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Strobed IOM-2 Bit Clock. Register SDS_CONF programmed to 01H . 88
Examples of MONITOR Channel Applications in IOM -2 TE Mode . . . 89
MONITOR Channel Protocol (IOM-2) . . . . . . . . . . . . . . . . . . . . . . . . . 91
Monitor Channel, Transmission Abort requested by the Receiver. . . . 94
Monitor Channel, Transmission Abort requested by the Transmitter. . 94
Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . . 95
MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
CIC Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Applications of TIC Bus in IOM-2 Bus Configuration . . . . . . . . . . . . . 101
Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . 102
Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . 103
D-Channel Access Control on the S-Interface . . . . . . . . . . . . . . . . . . 104
Deactivation of the IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Activation of the IOM-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
RFIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Data Reception Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Reception Sequence Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Transmission Sequence Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Interrupt Status Registers of the HDLC Controllers . . . . . . . . . . . . . . 125
Layer 2 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Register Mapping of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . 128
Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 186
IOM-2 Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . 188
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Microprocessor Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
10
PSB 3186
PSF 3186
2000-08-23
Page