PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 124

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

PSB 3186
PSF 3186
Description of Functional Blocks
3.8.5
Extended Transparent Mode
This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent
mode fully transparent data transmission/reception without HDLC framing is performed
i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism.
This allows user specific protocol variations.
Transmitter
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOM-2 frame aligned and byte aligned, i.e. transmission starts in the first selected
channel (B1, B2, D, according to the setting of register DCI_CR in the IOM-2 Handler) of
the next IOM-2 frame.
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with an XPR interrupt
after sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the collision detection is enabled in D-channel (MODE.DIM = ’0x1’) the stop go bit (S/
G) can be used as clear to send indication as in any other mode. If the S/G bit is set to
’1’ (stop) during transmission the transmitter responds always with an XMR (transmit
message repeat) interrupt.
If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs
out of data then it will assert an XDU (transmit data underrun) interrupt.
Receiver
The reception is IOM-2 frame aligned and byte aligned, like transmission, i.e. reception
starts in the first selected channel (B1, B2, D, according to the setting of registers
DCI_CR in the IOM-2 Handler) of the next IOM-2 frame. The FIFO indications and
commands are the same as in others modes.
All incoming data bytes are stored in the RFIFOD and is additionally made available in
RSTAD. If the FIFO is full an RFO interrupt is asserted (EXMD.SRA = ’0’).
Note: In the extended transparent mode the EXMD register has to be set to ’xxx00000’
Data Sheet
124
2000-08-23