PSB3186FV1.4 Infineon Technologies, PSB3186FV1.4 Datasheet - Page 9

• Manufacturer Part Number: PSB3186FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV1.4

• Control Type: HDLC
• Data Rate: 192 Kbps
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

List of Figures
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Data Sheet
Logic Symbol of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Applications of the ISAC-SX TE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Configuration of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional Block Diagram of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . 27
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 34
Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ACL Indication of Activated Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . . 43
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 45
Data Delay between IOM-2 and S/T Interface . . . . . . . . . . . . . . . . . . . 48
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation 49
Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . . 50
Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . . 51
Connection of Line Transformers and Power Supply
to the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 54
Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Clock System of the ISAC-SX TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Phase Relationships of ISAC-SX TE Clock Signals . . . . . . . . . . . . . . 60
Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Layer-1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
State Transition Diagram (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
State Transition Diagram of Unconditional Transitions (TE) . . . . . . . . 66
Example of Activation/Deactivation Initiated by the Terminal . . . . . . . 72
IOM -2 Frame Structure in Terminal Mode . . . . . . . . . . . . . . . . . . . . 74
Architecture of the IOM Handler (Example Configuration). . . . . . . . . . 76
Data Access via CDAx1 and CDAx2 register pairs . . . . . . . . . . . . . . . 78
Examples for Data Access via CDAxy Registers
a) Looping Data
b) Shifting (Switching) Data
c) Shifting and Looping Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9
PSB 3186
PSF 3186
2000-08-23
Page