ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 90
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ADF7023-JBCPZ
Manufacturer Part Number
ADF7023-JBCPZ
Description
TXRX FSK/GFSK/MSK/GMSK 32LFCSP
Manufacturer
Analog Devices Inc
Series
-r
Datasheet
1.EVAL-ADF7023-JDB1Z.pdf
(100 pages)
Specifications of ADF7023-JBCPZ
Frequency
902MHz ~ 958MHz
Data Rate - Maximum
300kbps
Modulation Or Protocol
FSK, GFSK, GMSK, MSK
Applications
ISM
Power - Output
13.5dBm
Sensitivity
-116dBm
Voltage - Supply
2.2 V ~ 3.6 V
Current - Receiving
12.8mA
Current - Transmitting
32.1mA
Data Interface
PCB, Surface Mount
Memory Size
-
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
32-WFQFN Exposed Pad, CSP
Rf Ic Case Style
LFCSP
No. Of Pins
32
Supply Voltage Range
2.2V To 3.6V
Operating Temperature Range
-40°C To +85°C
Transmitting Current
32.1mA
Data Rate
300Kbps
Modulation Type
2FSK, GFSK, MSK
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
ADF7023-J
MCR REGISTER DESCRIPTION
The MCR register settings are not retained when the device enters the PHY_SLEEP state.
Table 96. 0x307: PA_LEVEL_MCR
Bit
[5:0]
Table 97. 0x30C: WUC_CONFIG_HIGH
Bit
[7]
[6]
[5]
[4]
[3]
[2:0]
Register WUC_CONFIG_LOW should never be written to without updating Register WUC_CONFIG_HIGH first.
Table 98. 0x30D: WUC_CONFIG_LOW
Bit
[7]
[6]
[5]
[4]
[3]
[2:1]
[0]
Updates to Register WUC_VALUE_HIGH become effective only after Register WUC_VALUE_LOW is written to.
Table 99. 0x30E: WUC_VALUE_HIGH
Bit
[7:0]
Name
WUC_TIMER_VALUE[15:8]
Name
Reserved
WUC_RCOSC_EN
WUC_XOSC32K_EN
WUC_CLKSEL
WUC_BBRAM_EN
Reserved
WUC_ARM
Name
PA_LEVEL_MCR
Name
Reserved
WUC_BGAP
WUC_LDO_SYNTH
WUC_LDO_DIG
WUC_XTO26M_EN
WUC_PRESCALER
R/W
W
W
W
W
W
W
W
W
W
W
W
R/W
W
R/W
R/W
R/W
W
W
Reset
0
Reset
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
Reset
0
Rev. 0 | Page 90 of 100
Description
Power amplifier level. If PA ramp is enabled, the PA ramps to this target
level. The PA level can be set in the 0 to 63 range. The PA level (with less
resolution) can also be set via the BBRAM; therefore, the MCR setting
should be used only if more resolution is required.
Description
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
WUC_PRESCALER
0
1
2
3
4
5
6
7
1: enable RCOSC32K
1: enable XOSC32K
Select the WUC timer clock source
1: enable wake-up on a WUC timeout event
Description
WUC timer reload value, Bits[15:8] of [15:0]. A wake-up event is triggered
when the WUC unit is enabled and the timer has counted down to 0. The
timer is clocked with the prescaler output rate. An update to this register
becomes effective only after WUC_VALUE_LOW is written. See Table 100.
Description
Set to 0
0: disable RCOSC32K
0: disable XOSC32K
1: RC 32.768 kHz oscillator
0: external crystal oscillator
1: enable power to the BBRAM during the PHY_SLEEP state
0: disable power to the BBRAM during the PHY_SLEEP state
Set to 0
0: disable wake-up on a WUC timeout event
32.768 kHz Divider
1
4
8
16
128
1034
81 2
65,536
Tick Period
30.52 μs
122.1 μs
244.1 μs
488.3 μs
3.91 ms
31.25 ms
250 ms
2000 ms