ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 4

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADF7023-J is a very low power, high performance, highly
integrated 2FSK/GFSK/MSK/GMSK transceiver designed for
operation in the 902 MHz to 958 MHz frequency band, which
covers the ARIB Standard T96 band at 950 MHz. Data rates
from 1 kbps to 300 kbps are supported.
The transmit RF synthesizer contains a VCO and a low noise
fractional-N phase locked loop (PLL) with an output channel
frequency resolution of 400 Hz. The VCO operates at twice the
fundamental frequency to reduce spurious emissions. The receive
and transmit synthesizer bandwidths are automatically, and
independently, configured to achieve optimum phase noise,
modulation quality, and settling time. The transmitter output
power is programmable from −20 dBm to +13.5 dBm, with
automatic PA ramping to meet transient spurious specifications.
The part possesses both single-ended and differential PAs, which
allow for Tx antenna diversity.
The receiver is exceptionally linear, achieving an IP3 specification
of −12.2 dBm and −11.5 dBm at maximum gain and minimum
gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm
at maximum gain and minimum gain, respectively. The receiver
achieves an interference blocking specification of 66 dB at a
±2 MHz offset and 74 dB at a ±10 MHz offset. Thus, the part
is extremely resilient to the presence of interferers in spectrally
noisy environments. The receiver features a novel, high speed,
AFC loop, allowing the PLL to find and correct any RF frequency
errors in the recovered packet. A patent pending image rejection
calibration scheme is available by downloading the image rejection
calibration firmware module to program RAM. The algorithm
does not require the use of an external RF source nor does it
require any user intervention once initiated. The results of the
RFIO_1N
1
RFIO_1P
GPIO REFERS TO PINS 17, 18, 19, 20, 25, AND 27.
RFO2
CREGRFx CREGVCO CREGSYNTH CREGDIGx
PA RAMP
PROFILE
LNA
PA
PA
DIVIDER
ADF7023-J
LOGAMP
FILTER
LOOP
RSSI/
ADCIN_ATB3
MODULATOR
CHARGE
DIVIDER
RBIAS
PUMP
BIAS
Σ-∆
8-BIT
ADC
ANALOG
Rev. 0 | Page 4 of 100
TEST
PFD
f
DEV
Figure 1.
DEMOD
AGC
26MHz OSC
FSK
ASK
CDR
AFC
GAUSSIAN
SENSOR
FILTER
XOSC32KN_ATB2
TEMP
calibration can be stored in nonvolatile memory for use on
subsequent power-ups of the transceiver.
The ADF7023-J operates with a power supply range of 2.2 V to
3.6 V and has very low power consumption in both Tx and Rx
modes, enabling long lifetimes in battery-operated systems while
maintaining excellent RF performance. The device can enter a
low power sleep mode in which the configuration settings are
retained in the battery backup random access memory (BBRAM).
The ADF7023-J features an ultralow power, on-chip,
communications processor. The communications processor,
which is an 8-bit RISC processor, performs the radio control,
packet management, and smart wake mode (SWM) functionality.
The communications processor eases the processing burden of
the companion processor by integrating the lower layers of a
typical communication protocol stack. The communications
processor also permits the download and execution of firmware
modules. Available modules include image rejection (IR)
calibration, advanced encryption standard (AES) encryption,
and Reed-Solomon coding. These firmware modules are included
in the Applications Software, which is available online at
ftp://ftp.analog.com/pub/RFL/ADF7023/.
The communications processor provides a simple command-based
radio control interface for the host processor. A single-byte command
transitions the radio between states or performs a radio function.
The communications processor provides support for generic
packet formats. The packet format is highly flexible and fully
programmable, thereby ensuring its compatibility with proprietary
packet profiles. In transmit mode, the communications processor
can be configured to add preamble, sync word, and CRC to the
PROCESSOR
BATTERY
MONITOR
8-BIT RISC
XOSC32KP_GP5_ATB1
WAKE-UP CONTROL
32kHz
OSC
TIMER UNIT
MCR RAM
256 BYTE
256 BYTE
4kB ROM
2kB RAM
PACKET
64 BYTE
BBRAM
MAC
RAM
RCOSC
32kHz
XOSC26N XOSC26P
DIVIDER
CLOCK
TEST
GPIO
26MHz
CTRL
DAC
IRQ
SPI
OSC
IRQ_GP3
CS
MISO
SCLK
MOSI
GPIO
1