ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 74

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J
APPLICATIONS INFORMATION
APPLICATION CIRCUIT
A typical application circuit for the ADF7023-J is shown in
Figure 83. All external components required for operation of
the device, excluding supply decoupling capacitors, are shown.
This example circuit uses a combined single-ended PA and LNA
match. Further details on matching topologies and different
host processor interfaces are given in the Host Processor
Interface section and the PA/LNA Matching section.
HOST PROCESSOR INTERFACE
The interface, when using packet mode, between the ADF7023-J
and the host processor is shown in Figure 81. In packet mode,
all communication between the host processor and the ADF7023-J
occurs on the SPI interface and the IRQ_GP3 pin. The interface
between the ADF7023-J and the host processor in sport mode is
shown in Figure 82. In sport mode, the transmit and receive data
interface consists of the GP0, GP1, and GP2 pins and a separate
interrupt is available on GP4, while the SPI interface is used for
memory access and issuing of commands.
CONNECTION
ANTENNA
HARMONIC
FILTER
PA/LNA
MATCH
Figure 83. Typical ADF7023-J Application Circuit Diagram
Rev. 0 | Page 74 of 100
VDD
1
2
3
4
5
6
7
8
CREGRF1
RBIAS
CREGRF2
RFIO_1P
RFIO_1N
RFO2
VDDBAT2
NC
ADF7023-J
ADF7023-J
Figure 81. Processor Interface in Packet Mode
ADF7023-J
Figure 82. Processor Interface in Sport Mode
GND PAD
25
25
IRQ_GP3
IRQ_GP3
SCLK
MOSI
MISO
SCLK
MOSI
MISO
GP2
GP1
GP0
GP2
GP1
GP0
CS
CS
32kHz XTAL (OPTIONAL)
26MHz XTAL
17
24
23
22
21
20
19
18
24
23
22
21
20
19
18
17
IRQ_GP3
V
V
DD
SCLK
MOSI
MISO
DD
GP2
GP1
GP0
CS
17
24
23
22
21
20
19
18
IRQ
GPIO
MOSI
SCLK
MISO
IRQ
TxRxCLK
TxDATA
RxDATA
GPIO
MOSI
SCLK
MISO
IRQ
V
DD
GPIO
MOSI
SCLK
MISO
IRQ