ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 85

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 73. 0x117: RADIO_CFG_11
Bit
[7:4]
[3:0]
Table 74. 0x118: IMAGE_REJECT_CAL_PHASE
Bit
[7]
[6:0]
Table 75. 0x119: IMAGE_REJECT_CAL_AMPLITUDE
Bit
[7]
[6:0]
Table 76. 0x11A: MODE_CONTROL
Bit
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Name
SWM_EN
BB_CAL
SWM_RSSI_QUAL
TX_TO_RX_AUTO_TURNAROUND
RX_TO_TX_AUTO_TURNAROUND
CUSTOM_TRX_SYNTH_LOCK_TIME_EN
EXT_LNA_EN
EXT_PA_EN
Name
AFC_KP
AFC_KI
Name
Reserved
IMAGE_REJECT_CAL_PHASE
Name
Reserved
IMAGE_REJECT_CAL_AMPLITUDE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
1: smart wake mode enabled.
0: smart wake mode disabled.
1: IF filter calibration enabled.
0: IF filter calibration disabled.
IF filter calibration is automatically performed on the transition from the PHY_OFF
state to the PHY_ON state if this bit is set.
1: RSSI qualify in low power mode enabled.
0: RSSI qualify in low power mode disabled.
If TX_TO_RX_AUTO_TURNAROUND = 1, the device automatically transitions to the
PHY_RX state at the end of a packet transmission, on the same RF channel
frequency. If TX_TO_RX_AUTO_TURNAROUND = 0, this operation is disabled.
TX_TO_RX_AUTO_TURNAROUND is only available in packet mode.
If RX_TO_TX_AUTO_TURNAROUND = 1, the device automatically transitions to the
PHY_TX state at the end of a valid packet reception, on the same RF channel
frequency. If RX_TO_TX_AUTO_TURNAROUND = 0, this operation is disabled.
RX_TO_TX_AUTO_TURNAROUND is only available in packet mode.
1: use the custom synthesizer lock time defined in Register 0x13E and Register 0x13F.
0: default synthesizer lock time.
1: external LNA enable signal on ATB4 is enabled. The signal is logic high while the
ADF7023-J is in the PHY_RX state and logic low while in any other nonsleep state.
0: external LNA enable signal on ATB4 is disabled.
1: external PA enable signal on ATB3 is enabled. The signal is logic high while the
ADF7023-J is in the PHY_TX state and logic low while in any other nonsleep state.
0: external PA enable signal on ADCIN_ATB3 is disabled.
Rev. 0 | Page 85 of 100
Description
Sets the AFC PI controller proportional gain in 2FSK/GFSK/MSK/GMSK; the
recommended value is 0x3.
AFC_KP
0
1
2
…
15
Sets the AFC PI controller integral gain in 2FSK/GFSK/MSK/GMSK; the
recommended value is 0x7.
AFC_KI
0
1
2
…
15
Sets the I/Q phase adjustment
Description
Sets the I/Q amplitude adjustment
Description
Set to 0
Set to 0
Proportional Gain
2
2
2
…
2
Integral Gain
2
2
2
…
2
0
1
2
15
0
1
2
15
ADF7023-J