ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 47

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J MEMORY MAP
This section describes the various memory locations used by
the ADF7023-J. The radio control, packet management, and
smart wake mode capabilities of the part are realized using an
integrated RISC processor, which executes instructions stored
in the embedded program ROM. There is also a local RAM,
subdivided into three sections, that is used as a data packet
buffer, both for transmitted and received data (packet RAM),
and for storing the radio and packet management configuration
(BBRAM and MCR). The RAM addresses of these memory
banks are 11 bits long.
BBRAM
The battery backup RAM contains the main radio and packet
management registers used to configure the radio. On application
of battery power to the ADF7023-J for the first time, the entire
BBRAM should be initialized by the host processor with the
appropriate settings. After the BBRAM is written to, the
CMD_CONFIG_DEV command should be issued to update the
radio and communications processor with the current BBRAM
settings. The CMD_CONFIG_DEV command can be issued in
the PHY_OFF state or the PHY_ON state only.
The BBRAM is used to maintain settings needed at wake-up from
sleep mode by the wake-up controller. Upon wake-up from sleep,
in smart wake mode, the BBRAM contents are read by the on-chip
processor to recover the packet management and radio parameters.
PROCESSOR
COMMS
CLOCK
SCLK
MISO
MOSI
CS
PROCESSOR
COMMS
ENGINE
8-BIT
RISC
SPI
Figure 57. ADF7023-J Memory Map
ARBITRATION
ADDRESS/
MEMORY
SPI/CP
DATA
MUX
Rev. 0 | Page 47 of 100
ADDRESS
[12:0]
MODEM CONFIGURATION RAM (MCR)
The 256-byte modem configuration RAM (MCR) contains the
various registers used for direct control or observation of the
physical layer radio blocks of the ADF7023-J. The contents of
the MCR are not retained in the PHY_SLEEP state.
PROGRAM ROM
The program ROM consists of 4 kB of nonvolatile memory. It
contains the firmware code for radio control, packet management,
and smart wake mode.
PROGRAM RAM
The program RAM consists of 2 kB of volatile memory. This
memory space is used for software modules, such as AES
encryption, IR calibration, and Reed-Solomon coding, which
are available from Analog Devices. The software modules are
downloaded to the program RAM memory space over the SPI
by the host processor. See the Downloadable Firmware Modules
section for details on loading a firmware module to program RAM.
INSTRUCTION/DATA
[7:0]
ADDRESS[10:0]
DATA[7:0]
PROGRAM
PROGRAM
RAM
ROM
2kB
4kB
0x3FF
0x300
0x13F
0x100
0x0FF
0x010
0x00F
0x000
ADDRESSES
RESERVED
256 BYTES
NOT USED
256 BYTES
64 BYTES
PACKET
BBRAM
11-BIT
MCR
RAM
ADF7023-J