ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 49

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SPI INTERFACE
GENERAL CHARACTERISTICS
The ADF7023-J is equipped with a 4-wire SPI interface, using
the SCLK, MISO, MOSI, and CS pins. The ADF7023-J always
acts as a slave to the host processor.
connection diagram between the processor and the ADF7023-J.
The diagram also shows the direction of the signal flow for each
pin. The SPI interface is active, and the MISO outputs enabled,
only while the
of eight bits, which is compatible with the SPI hardware of most
processors. The data transfer through the SPI interface occurs
with the most significant bit first. The MOSI input is sampled at
the rising edge of SCLK. As commands or data are shifted in
from the MOSI input at the SCLK rising edge, the status word
or data is shifted out at the MISO pin synchronous with the
SCLK clock falling edge. If CS is brought low, the most significant
bit of the status word appears on the MISO output without the
need for a rising clock edge on the SCLK input.
COMMAND ACCESS
The ADF7023-J is controlled through commands. Command
words are single octet instructions that control the state transitions
of the communications processor and access to the registers and
packet RAM. The complete list of valid commands is given in
the Command Reference section. Commands that have a CMD
prefix are handled by the communications processor. Memory
access commands have an SPI prefix and are handled by an
independent controller. Thus, SPI commands can be issued
independent of the state of the communications processor.
A command is initiated by bringing CS low and shifting in the
command word over the SPI, as shown in
are executed after
of the SCLK input. The latter condition occurs in the case of a
memory access command, in which case the command is executed
on the positive SCLK clock edge corresponding to the most
significant bit of the first parameter word. The CS input must
be brought high again after a command has been shifted into
the ADF7023-J to enable the recognition of successive
command words. This is because a single command can be
issued only during a CS low period (with the exception of a
double NOP command).
ADF7023-J
CS input is low. The interface uses a word length
Figure 59. SPI Interface Connections
CS goes high again or at the next positive edge
IRQ_GP3
SCLK
MOSI
MISO
CS
Figure 59
SCLK
GPIO
MOSI
MISO
IRQ
Figure 60
shows an example
PROCESSOR
. All commands
HOST
Rev. 0 | Page 49 of 100
STATUS WORD
The status word of the ADF7023-J is automatically returned
over the MISO each time a byte is transferred over the MOSI.
Shifting in double SPI_NOP commands (see Table 27) causes
the status word to be shifted out as shown in Figure 61. The
meaning of the various bit fields is illustrated in Table 25. The
FW_STATE variable can be used to read the current state of the
communications processor and is described in Table 26. If it is busy
performing an action or state transition, FW_STATE is busy.
The FW_STATE variable also indicates the current state of the radio.
The SPI_READY variable is used to indicate when the SPI is ready
for access. The CMD_READY variable is used to indicate when
the communications processor is ready to accept a new command.
The status word should be polled and the CMD_READY bit
examined before issuing a command to ensure that the
communications processor is ready to accept a new command.
It is not necessary to check the CMD_READY bit before issuing
a SPI memory access command. It is possible to queue one
command while the communications processor is busy. This
is discussed in the Command Queuing section.
The ADF7023-J interrupt handler can also be configured
to generate an interrupt signal on IRQ_GP3 when the
communications processor is ready to accept a new command
(CMD_READY in the INTERRUPT_SOURCE_1 register
[Address 0x337]) or when it has finished processing a command
(CMD_FINISHED in the INTERRUPT_SOURCE_1 register
[Address 0x337]).
Table 25. Status Word
Bit
[7]
[6]
[5]
[4:0]
MOSI
MISO
Figure 61. Reading the Status Word Using a Double SPI_NOP Command
MOSI
MISO
CS
CS
Name
SPI_READY
IRQ_STATUS
CMD_READY
FW_STATE
Figure 60. Command Write (No Parameters)
SPI_NOP
IGNORE
Description
0: SPI is not ready for access.
1: SPI is ready for access.
0: no pending interrupt condition.
1: pending interrupt condition (mirrors
the IRQ_GP3 pin).
0: the radio controller is not ready to
receive a radio controller command.
1: the radio controller is ready to receive a
radio controller command.
Indicates the ADF7023-J state (in Table 26).
IGNORE
CMD
SPI_NOP
STATUS
ADF7023-J