ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 61

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIRMWARE TIMER SETUP
The ADF7023-J wakes up from the PHY_SLEEP state at the rate
set by the WUC. A firmware timer, implemented by the on-chip
processor, can be used to count the number of hardware wake-ups
and generate an interrupt to the host processor. Thus, the
ADF7023-J can be used to handle the wake-up timing of the
host processor, reducing overall system power consumption.
To set up the firmware timer, the host processor must set a value
in the NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0]
registers (Address 0x104 and Address 0x105). This 16-bit value
represents the number of times the device wakes up before it
WUC Setting
WUC_CONFIG_LOW[7]
WUC_CONFIG_LOW[6]
WUC_CONFIG_LOW[5]
WUC_CONFIG_LOW[4]
WUC_CONFIG_LOW [3]
WUC_CONFIG_LOW[2:1]
WUC_CONFIG_LOW[0]
Name
Reserved
WUC_RCOSC_EN
WUC_XOSC32K_EN
WUC_CLKSEL
WUC_BBRAM_EN
Reserved
WUC_ARM
Rev. 0 | Page 61 of 100
Description
Set to 0.
1: enable.
0: disable RCOSC32K.
1: enable.
0: disable XOSC32K.
1: RC 32.768 kHz oscillator.
0: external crystal oscillator.
1: enable power to BBRAM during the PHY_SLEEP state.
0: disable power to BBRAM during the PHY_SLEEP state.
Set to 0.
1: enable wake-up on WUC timeout event.
0: disable wake-up on WUC timeout event.
interrupts the host processor. At each wake-up, the ADF7023-J
increments the NUMBER_OF_WAKEUPS[15:0] registers
(Address 0x102 and Address 103). If this value exceeds the value
set by the NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0]
registers, the NUMBER_OF_WAKEUPS[15:0] value is cleared
to 0. At this time, if the INTERRUPT_NUM_WAKEUPS bit in
the INTERRUPT_MASK_0 register (Address 0x100) is set, the
device asserts the IRQ_GP3 pin and enters the PHY_OFF state.
ADF7023-J