ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 41

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The address data is then compared against a list of known addresses
that are stored in BBRAM (Address 0x12B to Address 0x13D).
Each stored address byte has an associated mask byte, thereby
allowing matching of partial sections of the address bytes,
which is useful for checking broadcast addresses or a family of
addresses that have a unique identifier in the address sequence.
The format and placement of the address information in the
payload data should match the address check settings at the
receiver to ensure exact address detection and qualification.
Table 19 shows the register locations in the BBRAM that are
used for setup of the address checking. When Register 0x12A
(number of bytes in the first address field) is set to 0x00,
address checking is disabled.
Table 19. Address Check Register Setup
Address (BBRAM)
0x129, ADDRESS_MATCH_
OFFSET
0x12A, ADDRESS_LENGTH
0x12B
0x12C
0x12D
0x12E
…
1
The host processor should set the INTERRUPT_ADDRESS_
MATCH bit in the INTERRUPT_SOURCE_0 register
(Address 0x336) if an interrupt is required on the IRG_GP3
pin. Additional information on interrupts is contained in the
Interrupt Generation section.
Example Address Check
Consider a system with 32-bit address lengths, in which the first
byte is located in the 10
system also uses broadcast addresses in which the first byte is
always 0xAA. To match the exact address, 0xABCDEF01 or any
broadcast address in the form 0xAAXXXXXX, the ADF7023-J
must be configured as shown in Table 20.
bytes in the second address field.
N
ADR_1
PREAMBLE
= the number of bytes in the first address field; N
WORD
SYNC
ADDRESS_MATCH_OFFSET
Figure 55. Address Match Offset
th
byte of the received payload data. The
Description
Position of first address byte in the
received packet (first byte after
sync word = 0)
Number of bytes in the first
address field (N
Address 1 Match Byte 0
Address 1 Mask Byte 0
Address 1 Match Byte 1
Address 1 Mask Byte 1
…
Address 1 Match Byte N
Address 1 Mask Byte N
0x00 to end or N
address check sequence
PAYLOAD
ADDRESS
DATA
1
ADR_1
ADR_2
ADR_2
)
= the number of
for another
ADR_1
CRC
ADR_1
− 1
− 1
Rev. 0 | Page 41 of 100
Table 20. Example Address Check Configuration
BBRAM
Address
0x129
0x12A
0x12B
0x12C
0x12D
0x12E
0x12F
0x130
0x131
0x132
0x133
0x134
0x135
0x136
0x137
0x138
0x139
0x13A
0x13B
0x13C
0x13D
CRC
An optional CRC-16 can be appended to the packet by setting
CRC_EN =1 in the PACKET_LENGTH_CONTROL register
(Address 0x126). In receive mode, this bit enables CRC detection
on the received packet. A default polynomial is used if
PROG_CRC_EN = 0 in the SYMBOL_MODE register
(Address 0x11C). The default CRC polynomial is
Any other 16-bit polynomial can be used if PROG_CRC_EN =
1, and the polynomial is set in CRC_POLY_0 and CRC_POLY_1
(Address 0x11E and Address 0x11F, respectively). The setup of
the CRC is described in Table 21.
Table 21.CRC Setup
CRC_EN
Bit in the
PACKET_
LENGTH
CONTROL
Register
0
1
1
1
X = don’t care.
g(x) = x
16
0x09
0x04
0xAB
0xFF
0xCD
0xFF
0xEF
0xFF
0x01
0xFF
0x04
0xAA
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xXX
Value
PROG_
CRC_EN
Bit in the
SYMBOL_
MODE
Register
X
0
1
+ x
1
12
+ x
Description
Location in payload of the first address byte
Number of bytes in the first address field,
N
Address 1 Match Byte 0
Address 1 Mask Byte 0
Address 1 Match Byte 1
Address 1 Mask Byte 1
Address 1 Match Byte 2
Address 1 Mask Byte 2
Address 1 Match Byte 3
Address 1 Mask Byte 3
Number of bytes in the second address
field, N
Address 2 Match Byte 0
Address 2 Mask Byte 0
Address 2 Match Byte 1
Address 2 Mask Byte 1
Address 2 Match Byte 2
Address 2 Mask Byte 2
Address 2 Match Byte 3
Address 2 Mask Byte 3
End of addresses (indicated by 0x00)
Don’t care
5
+ 1
ADR_1
Description
CRC is disabled in transmit, and CRC
detection is disabled in receive.
CRC is enabled in transmit, and CRC
detection is enabled in receive, with
the default CRC polynomial.
CRC is enabled in transmit, and CRC
detection is enabled in receive, with
the CRC polynomial defined by
CRC_POLY_0 and CRC_POLY_1.
= 4
ADR_2
= 4
ADF7023-J