ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 45

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register
INTERRUPT_MASK_1,
Address 0x101
Table 24. Structure of the Interrupt Source Registers
Register
INTERRUPT_SOURCE_0,
Address: 0x336
INTERRUPT_SOURCE_1,
Address: 0x337
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Name
BATTERY_ALARM
CMD_READY
Reserved
WUC_TIMEOUT
Reserved
Reserved
SPI_READY
CMD_FINISHED
Name
INTERRUPT_NUM_WAKEUPS
INTERRUPT_SWM_RSSI_DET
INTERRUPT_AES_DONE
INTERRUPT_TX_EOF
INTERRUPT_ADDRESS_MATCH
INTERRUPT_CRC_CORRECT
INTERRUPT_SYNC_DETECT
INTERRUPT_PREAMBLE_DETECT
BATTERY_ALARM
CMD_READY
Reserved
WUC_TIMEOUT
Reserved
Reserved
SPI_READY
CMD_FINISHED
Rev. 0 | Page 45 of 100
Interrupt when the WUC has timed out
Interrupt when the SPI is ready for access
Asserted when a packet has finished transmitting (packet mode only)
Asserted when the WUC has timed out
Asserted when the SPI is ready for access
Description
Interrupt when the battery voltage has dropped below the threshold
value (BATTERY_MONITOR_THRESHOLD_VOLTAGE, Address 0x32D)
1: interrupt enabled; 0: interrupt disabled
Interrupt when the communications processor is ready to load a new
command; mirrors the CMD_READY bit of the status word
1: interrupt enabled; 0: interrupt disabled
1: interrupt enabled; 0: interrupt disabled
1: interrupt enabled; 0: interrupt disabled
Interrupt when the communications processor has finished
performing a command
1: interrupt enabled; 0: interrupt disabled
Interrupt Description
Asserted when the number of WUC wake-ups
(NUMBER_OF_WAKEUPS[15:0]) has reached the threshold
(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0])
Asserted when the measured RSSI during smart wake mode has
exceeded the RSSI threshold value (SWM_RSSI_THRESH,
Address 0x108)
Asserted when an AES encryption or decryption command is
complete; available only when the AES firmware module has been
loaded to the ADF7023-J program RAM
Asserted when a received packet has a valid address match (packet
mode only)
Asserted when a received packet has the correct CRC (packet mode only)
Asserted when a qualified sync word has been detected in the
received packet
Asserted when a qualified preamble has been detected in the
received packet
Asserted when the battery voltage has dropped below the threshold
value (BATTERY_MONITOR_THRESHOLD_VOLTAGE, Address 0x32D)
Asserted when the communications processor is ready to load a new
command; mirrors the CMD_READY bit of the status word
Asserted when the communications processor has finished
performing a command
ADF7023-J