ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 83
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ADF7023-JBCPZ
Manufacturer Part Number
ADF7023-JBCPZ
Description
TXRX FSK/GFSK/MSK/GMSK 32LFCSP
Manufacturer
Analog Devices Inc
Series
-r
Datasheet
1.EVAL-ADF7023-JDB1Z.pdf
(100 pages)
Specifications of ADF7023-JBCPZ
Frequency
902MHz ~ 958MHz
Data Rate - Maximum
300kbps
Modulation Or Protocol
FSK, GFSK, GMSK, MSK
Applications
ISM
Power - Output
13.5dBm
Sensitivity
-116dBm
Voltage - Supply
2.2 V ~ 3.6 V
Current - Receiving
12.8mA
Current - Transmitting
32.1mA
Data Interface
PCB, Surface Mount
Memory Size
-
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
32-WFQFN Exposed Pad, CSP
Rf Ic Case Style
LFCSP
No. Of Pins
32
Supply Voltage Range
2.2V To 3.6V
Operating Temperature Range
-40°C To +85°C
Transmitting Current
32.1mA
Data Rate
300Kbps
Modulation Type
2FSK, GFSK, MSK
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Table 69. 0x113: RADIO_CFG_7
Bit
[7:6]
[5:4]
[3:0]
Table 70. 0x114: RADIO_CFG_8
Bit
[7]
[6:3]
Name
PA_SINGLE_DIFF_SEL
PA_LEVEL
Name
AGC_LOCK_MODE
SYNTH_LUT_CONTROL
SYNTH_LUT_CONFIG_1
R/W
R/W
R/W
Description
PA_SINGLE_DIFF_SEL
0
1
Sets the PA output power. A value of zero sets the minimum RF output power, and a value of 15
sets the maximum PA output power. The PA level can also be set with finer resolution using the
PA_LEVEL_MCR setting (Address 0x307). The PA_LEVEL setting is related to the PA_LEVEL_MCR
setting by PA_LEVEL_MCR = 4 × PA_LEVEL + 3.
PA_LEVEL
0
1
2
15
R/W
R/W
R/W
R/W
Rev. 0 | Page 83 of 100
Description
0: free running
1: manual
2: hold
3: lock after preamble/sync word (only locks on a sync word if PREAMBLE_
MATCH = 0)
By default, the synthesizer loop bandwidth is automatically selected from
lookup tables (LUT) in ROM memory. A narrow bandwidth is selected in
receive to ensure optimum interference rejection, whereas in transmit, the
bandwidth is selected based on the data rate and modulation settings. For
the majority of applications, these automatically selected PLL loop
bandwidths are optimum. However, in some applications, it may be
necessary to use custom transmit or receive bandwidths, in which case,
various options exist, as follows.
SYNTH_LUT_CONTROL
0
1
2
3
Because packet RAM memory is lost in the PHY_SLEEP state, the custom
LUT for transmit must be reloaded to packet RAM after waking from the
PHY_SLEEP state.
If SYNTH_LUT_CONTROL = 0 or 2, set SYNTH_LUT_CONFIG_0 to 0. If
SYNTH_LUT_CONTROL = 1 or 3, this setting allows the receiver PLL loop
bandwidth to be changed to optimize the receiver local oscillator phase noise.
Set to:
PA
Single-ended PA enabled
Differential PA enabled
PA Level (PA_LEVEL_MCR)
Setting 3
Setting 7
Setting 11
Setting 63
Description
Use predefined transmit and receive LUTs. The
LUTs are automatically selected from ROM
memory on transitioning into the PHY_TX or
PHY_RX state.
Use custom receive LUT based on SYNTH_
LUT_CONFIG_0 and SYNTH_LUT_CONFIG_1. In
transmit, the predefined LUT in ROM is used.
Use a custom transmit LUT. The custom
transmit LUT must be written to the 0x10 to
0x18 packet RAM locations. In receive, the
predefined LUT in ROM is used.
Use a custom receive LUT based on SYNTH_
LUT_CONFIG_0 and SYNTH_LUT_CONFIG_1,
and use a custom transmit LUT. The custom
transmit LUT must be written to the 0x10 to
0x18 packet RAM locations.
ADF7023-J