ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 18

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J
Pin No.
21
22
23
24
25
26
27
28
29
30
31
32
Mnemonic
MISO
SCLK
MOSI
CS
GP4
CREGDIG2
XOSC32KP_GP5_ATB1
XOSC32KN_ATB2
VDDBAT1
ADCIN_ATB3
ATB4
ADCVREF
EPAD
The exposed package paddle must be connected to GND.
Description
Serial Port Master In/Slave Out.
Serial Port Clock.
Serial Port Master Out/Slave In.
Chip Select (Active Low). A pull-up resistor of 100 kΩ to V
processor from inadvertently waking the ADF7023-J from sleep.
Digital GPIO Test Pin 4.
Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this
pin and ground for regulator stability and noise rejection.
Digital GPIO Test Pin 5. A 32 kHz watch crystal can be connected between this pin and
XOSC32KN_ATB2. Analog Test Pin 1.
A 32 kHz watch crystal can be connected between this pin and XOSC32KP_GP5_ATB1. Analog Test
Pin 2.
Digital Power Supply Pin One. Decoupling capacitors to the ground plane should be placed as close
as possible to this pin.
Analog-to-Digital Converter Input. Can be configured as an external PA enable signal. Analog Test
Pin 3.
Analog Test Pin 4. Can be configured as an external LNA enable signal.
ADC Reference Output. A 220 nF capacitor should be placed between this pin and ground for
adequate noise rejection.
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is recommended to prevent the host