PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 69

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2.2
9.2.3
9.2.4
Pericom Semiconductor
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch,
bit 31=0). Time-to-preempt can be programmed to 8,16, 32, 64, or 128 (default is 32)
clocks.
If the current master occupies the bus and other masters are waiting, the current master
will be preempted by removing its grant (GNT#) after the next master waits for the time-
to-preempt.
SECONDARY BUS ARBITRATION USING AN EXTERNAL
ARBITER
The internal arbiter is disabled when the secondary bus central function control pin,
S_CFN#, is tied high. An external arbiter must then be used.
When S_CFN# is tied high, PI7C7300D, reconfigures four pins (two per port) to be
external request and grant pins. The S1_GNT#[0] and S2_GNT#[0] pins are reconfigured
to be the external request pins because they are output. The S1_REQ#[0] and
S2_REQ#[0] pins are reconfigured to be the external grant pins because they are input.
When an external arbiter is used, PI7C7300D uses the S1_GNT#[0] or S2_GNT#[0] pin
to request the secondary bus. When the reconfigured S1_REQ#[0] and S2_REQ#[0] pin
is asserted low after PI7C7300D has asserted S1_GNT#[0] or S2_GNT#[0]. PI7C7300D
initiates a transaction on the secondary bus one cycle later. If grant is asserted and
PI7C7300D has not asserted the request, PI7C7300D parks AD, CBE and PAR pins by
driving them to valid logic levels.
The unused secondary bus grants outputs, S_GNT#[7:1] and S_GNT#[6:1] are driven
high. The unused secondary bus requests inputs, S1_REQ#[7:1] and S2_REQ#[6:1],
should be pulled high.
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0]#, and PAR lines to a known value
while the bus is idle. In general, the device implementing the bus arbiter is responsible
for parking the bus or assigning another device to park the bus. A device parks the bus
when the bus is idle, its bus grant is asserted, and the device’s request is not asserted. The
AD and CBE signals should be driven first, with the PAR signal driven one cycle later.
PI7C7300D parks the primary bus only when P_GNT# is asserted, P_REQ# is de-
asserted, and the primary PCI bus is idle. When P_GNT# is de-asserted, PI7C7300D 3-
states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C7300D
is parking the primary PCI bus and wants to initiate a transaction on that bus, then
PI7C7300D can start the transaction on the next PCI clock cycle by asserting
P_FRAME# if P_GNT# is still asserted.
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the
last master that used the PCI bus. That is, PI7C7300D keeps the secondary bus grant
asserted to a particular master until a new secondary bus request comes along. After
reset, PI7C7300D parks the secondary bus at itself until transactions start occurring on
Page 69 of 107
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D