PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 6
PI7C7300DNAE
Manufacturer Part Number
PI7C7300DNAE
Description
IC PCI-PCI BRIDGE 3PORT 272-BGA
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C7300DNAE.pdf
(107 pages)
Specifications of PI7C7300DNAE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
272-PBGA
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
Supply Current (max)
660 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PI7C7300DNAE
Manufacturer:
Pericom
Quantity:
135
Company:
Part Number:
PI7C7300DNAE
Manufacturer:
MAX
Quantity:
5 510
6
7
8
9
10
11
12
Pericom Semiconductor
5.1
5.2
5.3
5.4
6.1
6.2
6.3
6.4
7.1
7.2
7.3
7.4
8.1
8.2
8.3
9.1
9.2
11.1
11.2
12.1
12.2
5.2.1
5.2.2
5.3.1
5.3.2
5.4.1
5.4.2
TRANSACTION ORDERING........................................................................................................ 49
ERROR HANDLING....................................................................................................................... 52
7.2.1
7.2.2
7.2.3
7.2.4
EXCLUSIVE ACCESS .................................................................................................................... 63
8.2.1
8.2.2
PCI BUS ARBITRATION............................................................................................................... 66
9.2.1
9.2.2
9.2.3
9.2.4
COMPACT PCI HOT SWAP ..................................................................................................... 70
CLOCKS ....................................................................................................................................... 70
RESET........................................................................................................................................... 71
ADDRESS RANGES................................................................................................................. 43
I/O ADDRESS DECODING...................................................................................................... 43
MEMORY ADDRESS DECODING ......................................................................................... 45
VGA SUPPORT......................................................................................................................... 48
TRANSACTIONS GOVERNED BY ORDERING RULES ..................................................... 49
GENERAL ORDERING GUIDELINES ................................................................................... 50
ORDERING RULES.................................................................................................................. 50
DATA SYNCHRONIZATION.................................................................................................. 52
ADDRESS PARITY ERRORS .................................................................................................. 52
DATA PARITY ERRORS ......................................................................................................... 53
DATA PARITY ERROR REPORTING SUMMARY .............................................................. 58
SYSTEM ERROR (SERR#) REPORTING ............................................................................... 63
CONCURRENT LOCKS ........................................................................................................... 64
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300D.................................................. 64
ENDING EXCLUSIVE ACCESS ............................................................................................. 65
PRIMARY PCI BUS ARBITRATION...................................................................................... 67
SECONDARY PCI BUS ARBITRATION................................................................................ 67
PRIMARY CLOCK INPUTS .................................................................................................... 70
SECONDARY CLOCK OUTPUTS .......................................................................................... 70
PRIMARY INTERFACE RESET.............................................................................................. 71
SECONDARY INTERFACE RESET........................................................................................ 71
I/O BASE AND LIMIT ADDRESS REGISTER................................................................... 44
ISA MODE.......................................................................................................................... 45
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS .............................. 46
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ....................... 47
VGA MODE........................................................................................................................ 48
VGA SNOOP MODE .......................................................................................................... 48
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE ............... 53
READ TRANSACTIONS ..................................................................................................... 53
DELAYED WRITE TRANSACTIONS ................................................................................. 54
POSTED WRITE TRANSACTIONS.................................................................................... 56
LOCKED TRANSACTIONS IN DOWSTREAM DIRECTION............................................ 64
LOCKED TRANSACTION IN UPSTREAM DIRECTION.................................................. 65
SECONDARY BUSARBITRATION USING THE INTERNAL ARBITER ........................... 67
PREEMPTION ................................................................................................................... 69
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER............................ 69
BUS PARKING................................................................................................................... 69
Page 6 of 107
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D