PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 50

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2
6.3
Pericom Semiconductor
Table 6-1 SUMMARY OF TRANSACTION ORDERING
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when
those transactions cross PI7C7300D.
The following general ordering guidelines govern transactions crossing PI7C7300D:
ORDERING RULES
Table 6-1 shows the ordering relationships of all the transactions and refers by number to
the ordering rules that follow.
Pass
Posted Write
Delayed Read Request
PI7C7300D does not combine separate write transactions into a single write
transaction—this optimization is best implemented in the originating master.
PI7C7300D does not merge bytes on separate masked write transactions to the same
DWORD address—this optimization is also best implemented in the originating
master.
PI7C7300D does not collapse sequential write transactions to the same address into
a single write transaction—the PCI Local Bus Specification does not permit this
combining of transactions.
The ordering relationship of a transaction with respect to other transactions is
determined when the transaction completes, that is, when a transaction ends with a
termination other than target retry.
Requests terminated with target retry can be accepted and completed in any order
with respect to other transactions that have been terminated with target retry. If the
order of completion of delayed requests is important, the initiator should not start a
second delayed transaction until the first one has been completed. If more than one
delayed transaction is initiated, the initiator should repeat all delayed transaction
requests, using some fairness algorithm. Repeating a delayed transaction cannot be
contingent on completion of another delayed transaction. Otherwise, a deadlock can
occur.
Write transactions flowing in one direction have no ordering requirements with
respect to write transactions flowing in the other direction. PI7C7300D can accept
posted write transactions on both interfaces at the same time, as well as initiate
posted write transactions on both interfaces at the same time.
The acceptance of a posted memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master.
This is true for PI7C7300D and must also be true for other bus agents. Otherwise, a
deadlock can occur.
PI7C7300D accepts posted write transactions, regardless of the state of completion
of any delayed transactions being forwarded across PI7C7300D.
Posted
Write
No
No
1
2
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Delayed
Read
Request
Yes
No
5
Delayed
Write
Request
Yes
No
5
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
Delayed Read
Completion
Yes
Yes
5
Delayed Write
Completion
Yes
Yes
PI7C7300D
5