PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 39

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9.3.1
4.9.3.2
Pericom Semiconductor
Table 4-7 DELAYED WRITE TARGET TERMINATION RESPONSE
Table 4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION
PI7C7300D handles these terminations in different ways, depending on the type of
transaction being performed.
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C7300D initiates a delayed write transaction, the type of target termination
received from the target can be passed back to the initiator. Table 4-7 shows the response
to each type of target termination that occurs during a delayed write transaction.
PI7C7300D repeats a delayed write transaction until one of the following conditions is
met:
PI7C7300D makes 2
of target retry.
After the PI7C7300D makes 2
on the target bus, PI7C7300D asserts P_SERR# if the SERR# enable bit (bit 8 of
command register for secondary bus S1 or S2) is set and the delayed-write-non- delivery
bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable
register (offset 64h). PI7C7300D will report system error. See Section 7.4 for a
description of system error conditions.
POSTED WRITE TARGET TERMINATION RESPONSE
When PI7C7300D initiates a posted write transaction, the target termination cannot be
passed back to the initiator. Table 4-8 shows the response to each type of target
termination that occurs during a posted write transaction.
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Target Termination
Normal
Target Retry
Target Disconnect
Normal termination (upon de-assertion of FRAME#)
Target retry
Target disconnect
Target abort
PI7C7300D completes at least one data transfer.
PI7C7300D receives a master abort.
PI7C7300D receives a target abort.
24
(default) or 2
Response
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
Repsonse
No additional action.
Repeating write transaction to target.
Initiate write transaction for delivering remaining posted write data.
Page 39 of 107
24
(default) attempts of the same delayed write trans-action
32
(maximum) write attempts resulting in a response
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D