PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 21

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4
4.1
Pericom Semiconductor
Table 4-1 PCI TRANSACTIONS
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across
PI7C7300D, and transaction termination. The PI7C7300D has three 128-byte buffers for
buffering of upstream and downstream transactions.
commands, and byte enables and are used for both read and write transactions.
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C7300D.
Table 4-1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C7300D initiates
transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when
PI7C7300D responds to transactions as a target, on the primary (P) and secondary (S1,
S2) buses.
Pin #
W15
W17
W19
Y1
Y3
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
Name
P_SERR#
P_AD[12]
P_AD[6]
AVCC
PLL_TM
P_RESET#
P_AD[31]
P_AD[25]
P_AD[21]
VSS
P_PERR#
P_AD[11]
P_AD[5]
Page 21 of 107
Type
POD
PB
PB
-
PI
PI
PB
PB
PB
-
PSTS
PB
PB
Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Pin #
W16
W18
W20
Y2
Y4
Y6
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
These hold addresses, data,
P_AD[9]
VDD
S_CFN#
BYPASS
VSS
P_AD[29]
P_IDSEL
P_DEVSEL#
Name
P_AD[14]
P_AD[18]
P_AD[13]
P_AD[8]
P_AD[2]
Responds as Target
Primary
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
PI7C7300D
-
PIU
-
-
PB
PI
N
N
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Type
PB
PB
PB
PSTS
PB
PB
PB
Secondary