PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 37

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.9
4.9.1
Pericom Semiconductor
TRANSACTION TERMINATION
This section describes how PI7C7300D returns transaction termination conditions back
to the initiator. The initiator can terminate transactions with one of the following types
of termination:
The target can terminate transactions with one of the following types of termination:
MASTER TERMINATION INITIATED BY PI7C7300D
PI7C7300D, as an initiator, uses normal termination if DEVSEL# is returned by target
within five clock cycles of PI7C7300D’s assertion of FRAME# on the target bus. As an
initiator, PI7C7300D terminates a transaction when the following conditions are met:
Normal termination
Normal termination occurs when the initiator de-asserts FRAME# at the beginning
of the last data phase, and de-asserts IRDY# at the end of the last data phase in
conjunction with either TRDY# or STOP# assertion from the target.
Master abort
A master abort occurs when no target response is detected. When the initiator does
not detect a DEVSEL# from the target within five clock cycles after asserting
FRAME#, the initiator terminates the transaction with a master abort. If FRAME# is
still asserted, the initiator de-asserts FRAME# on the next cycle, and then de-asserts
IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which
FRAME# de-asserts. If FRAME# is already de-asserted, IRDY# can be de-asserted
on the next clock cycle following detection of the master abort condition.
Normal termination
TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and
IRDY# asserted.
Target retry
STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase.
No data transfers occur during the transaction. This transaction must be repeated.
Target disconnect with data transfer
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer
of the transaction.
Target disconnect without data transfer
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data
transfers have been made. Indicates that no more data transfers will be made during
this transaction.
Target abort
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will
never be able to complete this transaction. DEVSEL# must be asserted for at least
one cycle during the transaction before the target abort is signaled.
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the
target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
Page 37 of 107
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D