PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet
PI7C7300DNAE
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PCI-to-PCI BRIDGE PI7C7300D Revision 1.01 ST 3545 North 1 Street, San Jose, CA 95134 Telephone: 1-877-PERICOM (1-877-737-4266) FAX: 408-435-1100 Internet: http://www.pericom.com ...
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... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product ...
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... REVISION HISTORY Revision Date 1.00 09/21/2004 1.01 11/21/2005 Pericom Semiconductor Description Initial release of datasheet Removed “Advance Information” from datasheet Renamed pin Y4 from BYPASS to BY_PASS Page 3 of 107 PI7C7300D 3-PORT PCI-TO-PCI BRIDGE November 2005 - Revision 1.01 ...
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... Pericom Semiconductor This page intentionally left blank. Page 4 of 107 PI7C7300D 3-PORT PCI-TO-PCI BRIDGE November 2005 - Revision 1.01 ...
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... TRANSACTION TERMINATION ........................................................................................... 37 4.9.1 MASTER TERMINATION INITIATED BY PI7C7300D..................................................... 37 4.9.2 MASTER ABORT RECEIVED BY PI7C7300D.................................................................. 38 4.9.3 TARGET TERMINATION RECEIVED BY PI7C7300D..................................................... 38 4.9.4 TARGET TERMINATION INITIATED BY PI7C7300D..................................................... 41 4.10 CONCURRENT MODE OPERATION..................................................................................... 42 5 ADDRESS DECODING .................................................................................................................. 42 Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 5 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... BUS PARKING................................................................................................................... 69 10 COMPACT PCI HOT SWAP ..................................................................................................... 70 11 CLOCKS ....................................................................................................................................... 70 11.1 PRIMARY CLOCK INPUTS .................................................................................................... 70 11.2 SECONDARY CLOCK OUTPUTS .......................................................................................... 70 12 RESET........................................................................................................................................... 71 12.1 PRIMARY INTERFACE RESET.............................................................................................. 71 12.2 SECONDARY INTERFACE RESET........................................................................................ 71 Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 6 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... MASTER TIMEOUT COUNTER REGISTER – OFFSET 74h ....................................... 91 14.1.39 RETRY COUNTER REGISTER – OFFSET 78h............................................................. 91 14.1.40 SAMPLING TIMER REGISTER – OFFSET 7Ch........................................................... 91 14.1.41 SECONDARY SUCCESSFUL I/O READ COUNTER REGISTER – OFFSET 80h ....... 91 Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 7 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... PRIMARY AND SECONDARY BUSES AT 66MH 17.5 PRIMARY AND SECONDARY BUSES AT 33MH 17.6 POWER CONSUMPTION ...................................................................................................... 106 18 272-PIN PBGA PACKAGE FIGURE ...................................................................................... 107 18.1 PART NUMBER ORDERING INFORMATION ................................................................... 107 Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE CLOCK TIMING .............................. 106 Z CLOCK TIMING .............................. 106 Z Page 8 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... LIST OF FIGURES F 9-1 SECONDARY ARBITER EXAMPLE.................................................................................. 68 IGURE F 16-1 TEST ACCESS PORT BLOCK DIAGRAM....................................................................... 98 IGURE F 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS .............................................. 105 IGURE F 18-1 272-PIN PBGA PACKAGE............................................................................................... 107 IGURE Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 9 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... This page intentionally left blank. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 10 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... INTRODUCTION PRODUCT DESCRIPTION The PI7C7300D is Pericom Semiconductor’s second-generation PCI-PCI Bridge and is an updated revision to the PI7C7300A designed to be fully compliant with the 32- bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C7300D supports only synchronous bus transactions between devices on the Primary Bus running at 33MHz to 66MHz and the Secondary Buses operating at either 33MHz or 66MHz ...
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... BLOCK DIAGRAM BLOCK DIAGRAM Pericom Semiconductor Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE 3-PORT PCI-TO-PCI BRIDGE Page 12 of 107 Page 12 of 107 November 2005 - Revision 1.01 November 2005 - Revision 1.01 PI7C7300D PI7C7300D ...
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... PRIMARY BUS INTERFACE SIGNALS Name P_AD[31:0] P_CBE[3:0] P_PAR P_FRAME# Pericom Semiconductor Description PCI input (3.3V, 5V tolerant) PCI input (3.3V, 5V tolerant) with weak pull-up PCI input (3.3V, 5V tolerant) with weak pull-down PCI output (3.3V) PCI tri-state bidirectional (3.3V, 5V tolerant) PCI sustained tri-state bi-directional (Active LOW signal which must be driven ...
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... P_DEVSEL# P_STOP# P_LOCK# P_IDSEL P_PERR# P_SERR# P_REQ# P_GNT# P_RESET# Pericom Semiconductor Pin # Type Description V13 PSTS Primary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase not de-asserted until the end of the data phase ...
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... SECONDARY BUS INTERFACE SIGNALS Name S1_AD[31:0], S2_AD[31:0] S1_CBE[3:0], S2_CBE[3:0] S1_PAR, S2_PAR S1_FRAME#, S2_FRAME# Pericom Semiconductor Pin # Type Description V18 PI Primary Interface 66MHz Operation. This input is used to specify if PI7C7300D is capable of running at 66MHz. For 66MHz operation on the Primary bus, this signal should be pulled “HIGH”. For 33MHz operation on the Primary bus, this signal should be pulled “ ...
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... S1_REQ#[7:0], S2_REQ#[6:0] S1_GNT#[7:0] S2_GNT#[6:0] S1_RESET#, S2_RESET# S1_EN, S2_EN S1_M66EN, S2_M66EN Pericom Semiconductor Pin # Type Description H19, PSTS Secondary IRDY (Active LOW). Driven by the B2 initiator of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase not de-asserted until the end of the data phase ...
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... PLL_TM S_CLKIN SCAN_TM# SCAN_EN 3.6 COMPACT PCI HOT-SWAP SIGNALS Name LOO HS_SW# Pericom Semiconductor Pin # Type Description Y2 PIU Secondary Bus Central Function Control Pin. When tied LOW, it enables the internal arbiter. When tied HIGH, an external arbiter must be used. S1_REQ#[0] or S2_REQ#[0] is reconfigured to be the secondary bus grant input, and S1_GNT#[0] or S2_GNT#[0] is reconfigured to be the secondary bus request output ...
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... AGND 3.9 PI7C7300D PBGA PIN LIST Pin # Name A1 S2_CBE[2] A3 VSS A5 VSS Pericom Semiconductor Pin # Type Description U6 PI Hot Swap Enable. To enable Hot Swap Friendly support, this signal should be pulled HIGH. R4 POD Hot Swap Status Indicator. The output of ENUM# indicates to the system that an insertion has occurred of that an extraction is about to occur ...
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... G19 S1_AD[16] H1 S2_AD[30] H3 S2_AD[28] H17 VSS H19 S1_IRDY# J1 S2_CLKOUT[0] J3 VDD J9 VSS J11 VSS J17 S1_PERR# J19 S1_STOP# K1 S2_REQ#[1] Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Pin # Name PB A8 VSS PB A10 VSS PTS A12 S1_REQ#[6] PTS A14 S1_GNT#[4] - A16 S1_REQ#[2] - A18 S1_CLKOUT[1] PTS ...
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... P_CBE[3] V11 P_AD[20] V13 P_IRDY# V15 VDD V17 VSS V19 P_CBE[0] W1 TMS W3 S1_EN W5 S2_M66EN W7 P_AD[30] W9 P_AD[24] W11 VSS W13 P_FRAME# Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Pin # Name PIU K4 VSS - K10 VSS - K12 VSS PB K18 S1_PAR - K20 S1_SERR S2_CLKOUT[1] PTS L4 S2_GNT#[2] ...
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... Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write and Invalidate Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Pin # Name POD W16 P_AD[14] PB W18 P_AD[9] PB W20 VDD - ...
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... Dual address transactions falling outside the prefetchable address range are forwarded upstream, but not downstream. Prefetching and posting are performed in a manner consistent with the guidelines given in this specification for each type of memory transaction in prefetchable memory space. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 22 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... Table 4-2 shows the method of forwarding used for each type of write operation. Table 4-2 WRITE TRANSACTION FORWARDING Type of Transaction Memory Write Memory Write and Invalidate Memory Write to VGA memory I/O Write Type 1 Configuration Write Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type of Forwarding Posted (except VGA memory) Posted Delayed Delayed Delayed Page 23 of 107 November 2005 - Revision 1 ...
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... The master latency timer expires, and PI7C7300D no longer has the target bus grant (PI7C7300D starts another transaction to deliver remaining write data). Section 4.9.3.2 provides detailed information about how PI7C7300D responds to target termination during posted write transactions. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 24 of 107 November 2005 - Revision 1.01 ...
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... PI7C7300D claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, PI7C7300D also asserts STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE 24 (default Page 25 of 107 November 2005 - Revision 1 ...
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... PI7C7300D continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, PI7C7300D returns a target disconnect to the initiator. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Condition Aligned Address Boundary ...
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... DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions, PI7C7300D forwards the read byte enable information for the data phase. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 27 of 107 November 2005 - Revision 1 ...
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... Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address boundary, or until the initiator de-asserts FRAME#. Section 4.7.6 describes flow- through mode during read operations. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 28 of 107 November 2005 - Revision 1.01 ...
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... Configuration Read I/O Read Memory Read Memory Read Memory Read Memory Read Line Memory Read Line Memory Read Multiple Memory Read Multiple - does not matter prefetchable or non-prefetchable * don’t care Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Address Space Cache Line Size (CLS ...
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... See Section 7.4 for information on the assertion of P_SERR#. Once PI7C7300D receives DEVSEL# and TRDY# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite inter-face, before terminating the Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Read Behavior ...
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... The PI7C7300D can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of DWORD transferred during a delayed read transaction depends on the conditions given in Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 31 of 107 November 2005 - Revision 1 ...
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... See Section 6 for a discussion of how delayed read transactions are ordered when crossing PI7C7300D. 4.7.7 FAST BACK-TO-BACK READ TRANSACTION Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE 15 default), PI7C7300D discards the read transaction and Page 32 of 107 November 2005 - Revision 1 ...
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... Function code is either 0 for configuration space of S1 for configuration space PI7C7300D is a multi-function device. PI7C7300D limits all configuration access to a single DWORD data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 33 of 107 November 2005 - Revision 1.01 ...
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... IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits P_AD[15:11]. Table 4-6 presents the mapping that PI7C7300D uses. Table 4-6 DEVICE NUMBER TO IDSEL S1_AD OR S2_AD PIN MAPPING Device Number Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE P_AD[15:11] Secondary IDSEL ...
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... The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The bus command is a configuration read or write transaction. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE 00000 0000 0000 0000 0001 ...
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... PI7C7300D responds with TRDY# to the next attempt of the con-figuration transaction from the initiator. If more than one data transfer is requested, PI7C7300D responds with a target disconnect operation during the first data phase. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 36 of 107 November 2005 - Revision 1.01 ...
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... PI7C7300D terminates a transaction when the following conditions are met: During a delayed write transaction, a single DWORD is delivered. During a non-prefetchable read transaction, a single DWORD is transferred from the target. During a prefetchable read transaction, a pre-fetch boundary is reached. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 37 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... TARGET TERMINATION RECEIVED BY PI7C7300D When PI7C7300D initiates a transaction on the target bus and the target responds with DEVSEL#, the target can end the transaction with one of the following types of termination: Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 38 of 107 November 2005 - Revision 1.01 ...
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... Table 4-8 shows the response to each type of target termination that occurs during a posted write transaction. Table 4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION Target Termination Normal Target Retry Target Disconnect Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE 24 32 (default (maximum) write attempts resulting in a response Response Returning disconnect to initiator with first data transfer only if multiple data phases requested ...
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... PI7C7300D asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or S2) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Repsonse Set received-target-abort bit in the target interface status register ...
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... The posted write data buffer does not have enough space for address and at least one DWORD of write data. A locked sequence is being propagated across PI7C7300D, and the write transaction is not a locked transaction. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 41 of 107 November 2005 - Revision 1.01 ...
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... PI7C7300D uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 42 of 107 November 2005 - Revision 1.01 ...
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... The master-enable bit also allows upstream forwarding of memory transactions set. CAUTION If any configuration state affecting I/O transaction forwarding is changed by a configuration write operation on the primary bus at the same time that I/O Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 43 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... I/O space. Write these registers with their appropriate values before setting either the I/O enable bit or the master enable bit in the command register in configuration space. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 44 of 107 November 2005 - Revision 1 ...
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... VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 45 of 107 November 2005 - Revision 1 ...
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... To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 46 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... The entire base value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. Therefore, to disable the address range, the upper Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 47 of 107 November 2005 - Revision 1 ...
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... VGA compatibility mode previously described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliases every 1KB throughout the first 64KB of I/O space. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 48 of 107 November 2005 - Revision 1 ...
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... PI7C7300D does not combine or merge write transactions: Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 49 of 107 November 2005 - Revision 1.01 ...
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... ORDERING RULES Table 6-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Table 6-1 SUMMARY OF TRANSACTION ORDERING Pass Posted Write Delayed Read Request Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Posted Delayed Delayed Write Read Write ...
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... Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Posted Delayed ...
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... PI7C7300D. PI7C7300D sets the detected parity error bit in the status register. PI7C7300D asserts P_SERR# and sets signaled system error bit in the status register, if both the following conditions are met: Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 52 of 107 November 2005 - Revision 1.01 ...
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... PERR#. For downstream transactions, when PI7C7300D detects a read data parity error on the secondary bus, the following events occur: Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 53 of 107 November 2005 - Revision 1.01 ...
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... When PI7C7300D detects a parity error on the write data for the initial delayed write request transaction, the following events occur: Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 54 of 107 November 2005 - Revision 1 ...
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... PI7C7300D has write status to return, the following events occur: PI7C7300D first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary interface parity-error-response bit is set in the command register. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 55 of 107 November 2005 - Revision 1.01 ...
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... PI7C7300D sets the parity error detected bit in the status register of the primary interface. PI7C7300D captures and forwards the bad parity condition to the secondary bus. PI7C7300D completes the transaction normally. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 56 of 107 November 2005 - Revision 1.01 ...
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... Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. If the parity error has forwarded from the initiating bus to the target bus, P_SERR# will not be asserted. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 57 of 107 November 2005 - Revision 1.01 ...
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... Table 7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT Secondary Detected Parity Error Bit don’t care Pericom Semiconductor Transaction Type Direction Read Downstream Read Downstream Read Upstream Read Upstream Posted Write Downstream Posted Write Downstream Posted Write Upstream Posted Write ...
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... Table 7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED BIT Secondary Detected Parity Detected Bit don’t care Pericom Semiconductor Transaction Type Direction Read Downstream Read Downstream Read Upstream Read Upstream Posted Write Downstream Posted Write Downstream Posted Write Upstream Posted Write ...
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... X = don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. Pericom Semiconductor Transaction Type Direction Read Downstream Read Downstream Read Upstream Read Upstream Posted Write Downstream Posted Write Downstream Posted Write ...
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... The parity error response bit must be set in the bridge control register of secondary interface. PI7C7300D detects a data parity error on the secondary bus or detects P_PERR# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 61 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... X = don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus. Pericom Semiconductor Transaction Type Direction Read Downstream Read ...
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... EXCLUSIVE ACCESS This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross PI7C7300D. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE 24 (default) attempts to deliver (2 24 ...
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... PI7C7300D. PI7C7300D allows any transactions queued before the locked transaction to complete before initiating the locked transaction. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 64 of 107 November 2005 - Revision 1 ...
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... LOCKED TRANSACTION IN UPSTREAM DIRECTION PI7C7300D ignores upstream lock and transactions. PI7C7300D will pass these transactions as normal transactions without lock established. 8.3 ENDING EXCLUSIVE ACCESS Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 65 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... For the secondary PCI bus, PI7C7300D implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus arbitration. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 66 of 107 November 2005 - Revision 1.01 ...
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... PI7C7300D, are in the high priority group, and five masters are in the low priority group. Using this example, if all requests are always asserted, the highest priority rotates among Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 67 of 107 November 2005 - Revision 1 ...
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... PCI clock cycle later. If the secondary PCI bus is busy, that is, either S1_FRAME# (S2_FRAME#) or S1_IRDY# (S2_IRDY#) is asserted, the arbiter can de-assert one grant and assert another grant during the same PCI clock cycle. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 68 of 107 November 2005 - Revision 1.01 ...
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... PCI bus. That is, PI7C7300D keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. After reset, PI7C7300D parks the secondary bus at itself until transactions start occurring on Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 69 of 107 November 2005 - Revision 1 ...
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... The S_CLKOUT[15:0] outputs are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of 0ns. This is the rule for using secondary clocks: Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE from Early Power ...
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... S1_CBE[3:0]#, S1_PAR (S2_AD, S2_CBE[3:0]#, S2_PAR) are driven low for the duration of S1_RESET# (S2_RESET#) assertion. All posted write and delayed transaction data buffers are reset. Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE rhfa Page 71 of 107 November 2005 - Revision 1 ...
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... P_CBE [3:0] # 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Command Action Interrupt Ignore Acknowledge Special Cycle Do not claim. Ignore. I/O Read 1. If address is within pass through I/O range, claim and pass through. ...
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... As PI7C7300D supports two secondary interfaces, it has two sets of configuration registers that are almost identical and accessed through different function numbers. PCI configuration defines a 64-byte space (configuration header) to define various attributes of the PCI-to-PCI Bridge as shown below. There are two configuration registers: Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Command Action 1 ...
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... Configuration Register 1 and Configuration Register 2 corresponding to Secondary Bus 1 and Secondary Bus 2 interfaces respectively. The configuration for the Primary interface is implemented through Configuration Register 1. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 74 of 107 November 2005 - Revision 1.01 PI7C7300D ...
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... Upstream ( Memory Limit Master Timeout Counter Chassis Number Hot Swap Control and Status 14.1.1 VENDOR ID REGISTER – OFFSET 00h Bit Function 15:0 Vendor ID Pericom Semiconductor 23-16 15-8 Status Class Code Header Type Primary Latency Timer Reserved Reserved Subordinate Bus Secondary Bus ...
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... Enable Special Cycle 3 Enable Memory Write 4 And Invalidate Enable VGA Palette 5 Snoop Enable Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description R/O Identifies this device as the PI7C7300D. Hardwired as 71E2h. Type Description R/O Identifies this device as the PI7C7300D. Hardwired as 71E3h. Type Description Controls response to I/O access on the primary interface ...
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... Fast Back-to- Back Capable 24 Data Parity Error Detected 26:25 DEVSEL# timing Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Controls response to parity errors 0: PI7C7300D may ignore any parity errors that it detects and continue normal operation R/W 1: PI7C7300D must take its normal action when a parity error is ...
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... Cache Line Size 14.1.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch Bit Function 15:8 Primary Latency timer Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description R/WC Set to 1 (by a target device) whenever a target abort cycle occurs Reset to 0 R/WC Set to 1 (by a master device) whenever transactions are terminated ...
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... Subordinate (S1 or S2) Bus Number 14.1.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h Bit Function 31:24 Secondary Latency Timer Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description R/O Read as 81h to designate function 0 (multiple function PCI-to-PCI bridge for secondary bus S1) Type Description R/O Read as 01h to designate function 1 (single function PCI-to-PCI ...
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... Back Capable Data Parity Error 24 Detected DEVSEL# 26:25 timing Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description R/O Read as 01h to indicate 32-bit I/O addressing R/W Defines the bottom address of the I/O address range for the bridge to determine when to forward I/O transactions from one interface to the other ...
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... MEMORY LIMIT REGISTER – OFFSET 20h Bit Function 19:16 31:20 Memory Limit Address [31:20] Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Set to 1 (by a target device) whenever a target abort cycle occurs on its secondary (S1 or S2) interface R/WC Reset to 0 Set to 1 (by a master device) whenever transactions on its secondary ...
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... PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch Bit Function 31:0 Prefetchable Memory Limit Address, Upper 32-bits [63:32] Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description R/O Indicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing Reset to 1 R/W ...
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... BRIDGE CONTROL REGISTER – OFFSET 3Ch Bit Function 16 Parity Error Response 17 S1_SERR# enable Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description R/W Defines the upper 16-bits of a 32-bit bottom address of an address range for the bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0 ...
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... Master Timeout Status 27 Discard Timer P_SERR# enable 31-28 Reserved Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description R/W Modifies the bridge’s response to ISA I/O addresses, applying only to those addresses falling within the I/O base and limit address registers and within the first 64KB or PCI I/O space. ...
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... Control 8:5 Reserved 10:9 Test Mode For All Counters at S2 15:11 Reserved Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description R/O Reserved. Returns 0 when read. Reset to 0 R/W Controls when the bridge (as a target) disconnects memory write transactions. 0: memory write disconnects at 4KB aligned address boundary ...
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... HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch Bit Function Hot Swap Time 27:0 Slot Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description R/W Each bit controls whether a secondary bus master is assigned to the high priority group or the low priority group. ...
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... UPSTREAM ( MEMORY BASE UPPER 32-BITS REGISTER – OFFSET 54h Bit Function Upstream 31:0 Memory Base Address Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Sets the number of clocks for time-to-preempt after another master request. 000: 32 clocks 001: 8 clocks R/W 010: 16 clocks ...
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... Non-Delivery Target Abort 3 During Posted Write Master Abort On 4 Posted Write Delayed Write 5 Non-Delivery Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Defines bits [63:32] of the upstream memory limit R/W Reset to 0 Type Description R/O Reserved. Returns 0 when read. Reset to 0 Controls PI7C7300D’s ability to assert P_SERR# when it is unable to ...
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... PORT OPTION REGISTER – OFFSET 74h Bit Function 0 Reserved Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Controls PI7C7300D’s ability to assert P_SERR# when it is unable to transfer any read data from the target after 2 0: P_SERR# is asserted if this event occurs and the SERR# enable bit ...
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... Enable Primary 11 To Hold Request Longer 15:12 Reserved Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Controls PI7C7300D’s detection mechanism for matching memory read retry cycles from the initiator on the primary interface 0: exact matching for non-posted memory write retry cycles from ...
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... SECONDARY SUCCESSFUL I/O WRITE COUNTER REGISTER – OFFSET 84h Bit Function Successful I/O 31:0 Write Counts Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Holds the maximum number of PCI clocks that PI7C7300D will wait for initiator to retry the same cycle before reporting timeout. Master R/W 10 timeout occurs after 2 PCI clocks ...
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... PRIMARY SUCCESSFUL MEMORY READ COUNTER REGISTER – OFFSET 98h Bit Function Successful Memory Read 31:0 Counts on Primary Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Stores the successful memory read count and is updated when the sampling timer is active. R/W Reset to 0 Type ...
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... Reserved 14.1.52 CHASSIS NUMBER REGISTER – OFFSET B0h Bit Function Chassis Number 31:24 Register Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Stores the successful memory write count on Primary and is updated when the sampling timer is active. R/W Reset to 0 Type Description ...
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... Reserved 15 BRIDGE BEHAVIOR A PCI cycle is initiated by asserting the FRAME# signal bridge, there are a number of possibilities. Those possibilities are summarized in the table below: Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Description Capability ID for Hot Swap 00h: Reserved 01h: PCI Power Management (PCIPM) ...
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... Cycle type shown on each row is the subsequent cycle after the previous shown on the column. Can Row Pass Column? PMW (Row 1) DRR (Row 2) DWR (Row 3) DRC (Row 4) Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Target Response Target on Primary PI7C7300D does not respond. It detects this situation by decoding the address as ...
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... Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master Abort. When the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a Master Abort. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Yes Yes ...
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... TAP pins, instruction register, test data registers and TAP controller. Error! Reference source not found. illustrates how these pieces fit together to form the JTAG unit. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 97 of 107 November 2005 - Revision 1 ...
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... When a new instruction is shifted in through TDI, the value 1101(binary) is always shifted out through TDO, least significant bit first. This helps identify instructions in a long chain of serial data from several devices. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 98 of 107 November 2005 - Revision 1 ...
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... TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register’s most significant bit. TDO is connected to the least significant bit. Data is shifted one bit position within the register towards TDO on Pericom Semiconductor Instruction Name Instruction Code ...
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... TCK controls the sequence of state changes. The TAP controller is initialized after power-up by applying a low to the TRST# pin. In addition, the TAP controller can be initialized by applying a high signal level on the TMS input for a minimum of five TCK periods. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Page 100 of 107 November 2005 - Revision 1.01 ...
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... P_IDSEL 38 P_AD[21] 39 P_AD[21] 40 P_AD[20] 41 P_AD[20] 42 P_AD[19] 43 P_AD[19] 44 P_AD[18] 45 P_AD[18] 46 P_AD[17] 47 P_AD[17] 48 P_AD[16] 49 P_AD[16] 50 P_CBE[2] 51 P_CBE[2] Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Order Pin Names output 60 P_STOP# control 61 P_PERR# input 62 P_PERR# input 63 P_LOCK# input 64 P_SERR# input 65 P_SERR# input 66 P_AD[13] input 67 P_AD[13] input ...
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... S1_CBE[2] 164 S1_CBE[2] 165 S1_AD[19] 166 S1_AD[19] 167 S1_CBE[3] 168 S1_CBE[3] 169 S1_AD[23] 170 S1_AD[23] 171 S1_AD[26] Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Order Pin Names bidir 112 S1_AD[5] control 113 S1_AD[3] bidir 114 S1_AD[3] control 115 S1_AD[4] bidir 116 ...
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... S2_AD[22] 280 S2_AD[24] 281 S2_AD[24] 17 ELECTRICAL AND TIMING SPECIFICATIONS 17.1 MAXIMUM RATINGS (Above which the useful life may be impaired. For user guidelines, not tested). Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Type Order Pin Names control 234 S2_AD[9] bidir 235 S2_AD[11] control ...
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... P_RESET#, S1_AD[31:0], S2_AD[31:0], S1_CBE[3:0], S2_CBE[3:0], S1_PAR, S2_PAR, S1_FRAME#, S2_FRAME#, S1_IRDY#, S2_IRDY#, S1_TRDY#, S2_TRDY#, S1_DEVSEL#, S2_DEVSEL#, S1_STOP#, S2_STOP#, S1_LOCK#, S2_LOCK#, S1_PERR#, S2_PERR#, S1_SERR#, S2_SERR#, S1_REQ[7:0]#, S2_REQ[6:0]#, S1_GNT[7:0]#, S2_GNT[6:0], S1_RESET#, S2_RESET#, S1_EN, S2_EN, HSLED, HS_SW#, HS_EN, ENUM#. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE , V only Condition Min ...
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... P_TRDY#, P_LOCK#, P_DEVSEL#, P_STOP#, P_IDSEL, S1_AD, S1_CBE#, S1_PAR, S1_PERR#, S1_SERR#, S1_FRAME#, S1_IRDY#, S1_TRDY#, S1_LOCK#, S1_devsel#, S1_STOP#, S2_AD, S2_CBE#, S2_PAR, S2_PERR#, S2_SERR#, S2_FRAME#, S2_IRDY#, S2_TRDY#, S2_LOCK#, S2_DEVSEL#, and S2_STOP#. 4. REQ# signals have a setup of 10 and GNT# signals have a setup of 12. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE 66 MHz Min. 1,2,3 3 ...
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... PCLK, S2_CLKOUT[6:0] LOW time LOW 17.6 POWER CONSUMPTION Parameter Power Consumption Supply Current Note: Typical values are at VCC = 3.3V 25°C, and all three ports running at 66MHz. Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE Condition 20pF load 20pF load Condition 20pF load 20pF load Typical ...
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... PBGA PACKAGE FIGURE Figure 18-1 272-PIN PBGA PACKAGE TOP Thermal Characteristics can be found on the web: 18.1 PART NUMBER ORDERING INFORMATION Part Number PI7C7300DNA PI7C7300DNAE Pericom Semiconductor 3-PORT PCI-TO-PCI BRIDGE BOTTOM http://www.pericom.com/packaging/mechanicals.php Pin – Package Temperature 272 – PBGA -40°C to 85°C 272 – ...