AD9929BBCZ Analog Devices Inc, AD9929BBCZ Datasheet - Page 58

• Manufacturer Part Number: AD9929BBCZ
• Description: IC CCD SIGNAL PROCESSOR 64-BGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9929BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9929
APPLICATIONS WHERE THE CLI CLOCK FREQUENCY CHANGES DURING OPERATION
The AD9929 must be reset, as described in Figure 69, if the CLI
clock frequency is changed during operation. The DCLK1
(REGISTER)
SERIAL PROGRAMMING STEPS MUST BE FOLLOWED WHEN THE CLI CLOCK FREQUENCY CHANGES
1. OUTCONT_REG = 0
2. DIG_STBY = 0
3. DIG_STBY = 1
4. OUTCONT_REG = 1
NOTES ABOUT REGIONS A, B, AND C
1
2
3
4
t
*IT TAKES 4 CLI CLOCK CYCLES FROM WHEN OUTCONT GOES HIGH UNTIL VD, HD AND DIGITAL OUTPUT DATA IS VALID.
1
DIGITAL OUTPUTS MAY BECOME INVALID IN REGION A
DIGITAL OUTPUTS ARE OUTPUT AS SHOWN IN REGION B
DCLK1 OUTPUT MAY BECOME INVALID IN REGION C
APPLICATIONS SHOULD NOT USE OUTPUT SIGNALS IN REGION C
DIG_STBY
(INTERNAL
OUTPUTS
= MINIMUM OF 2 CLI CLOCK CYCLES
OUTCONT
(OUTPUT)
(OUTPUT)
SIGNAL)
DCLK1I
WRITES
SERIAL
CL
HD
VD
Figure 69. Reset Sequence That Must Be Applied when Changing the CLI Clock Frequency During Operation
FAST
REGION A
1
(V1, V2, V3, V4 = VL), H2, STROBE, MSHUT
HD, VD, H1, (SUBCK = VH2)
REGION C
SLOW
Rev. A | Page 58 of 64
REGION B
output can become unstable if this reset sequence is not applied
after any changes in the CLI clock frequency.
t
1
2
3
4
FAST
t
DELAY
*