AD9929BBCZ Analog Devices Inc, AD9929BBCZ Datasheet - Page 30

• Manufacturer Part Number: AD9929BBCZ
• Description: IC CCD SIGNAL PROCESSOR 64-BGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9929BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9929
CONTROLLING CLPOB CLAMP PULSE OUTPUTS
The registers in Table 19 are used for programming the CLPOB
pulse. The CLPOB pulse is disabled in all CCD regions by
setting CLPCNT = 0. The CLPTOGx (x = 0, 1) are used to set
the CLPOB toggle positions. The CLPENx (x = 0, 1, 2, 3, and 4)
are used to enable or disable the CLPOB pulse separately in
each CCD region when CLPMODE = 0. The CLPEN registers
have no effect if CLPMODE = 1. In this case, the CLPOB pulse
is asserted in all CCD regions, regardless of the value set in the
CLPENx registers.
Figure 26 shows an example of the CLPOB pulse being disabled
in CCD Regions 1 and 3 by setting CLPEN1 = 1 and
CLPEN3 =1. Note that the CLPOB pulse remains disabled in
the first line of the following CCD region.
GRAY COUNTER
(INTERNAL)
CLPMASK
CLPOB
+ SET-UP
CLPOB
12-BIT
HD
VD
VD
HD
PROGRAMMING POSITIONS
1. SCP0 = 0 (FIXED), CLPEN0 = 1
2. SCP1 = 3, CLPEN1 = 0
3. SCP2 = 4, CLPEN2 = 1
4. SCP3 = 5, CLPEN3 = 0
5. SCP4 = 1, CLPEN4 = 1
NOTES
1. THE INTERNAL CLPMASK SIGNAL EXTENDS ONE EXTRA HD CYCLE FROM WHEN THE CLPMASK PERIOD CHANGES FROM LOW TO HIGH.
PROGRAMMABLE CLOCK POSITIONS
1. CLPTOG1 (SYS_REG (15))
2. CLPTOG2 (SYS_REG (15 AND 16))
AS A RESULT, ONE ADDITIONAL CLPOB PULSE IS MASKED AS SHOWN AT POSITIONS A AND B.
1
0
1
2
2
Figure 25. Location of CLPOB using CLPTOG1 and CLPTOG2 Registers.
3
4
Figure 26. CLPOB Outputs with CLPMODE = 0
5
6
Rev. A | Page 30 of 64
3
A
7
8
Table 20. SCP and CLPEN
SCP[4:1]
SCP0
SCP1
SCP2
SCP3
SCP4
1
SCP0 is not a programmable register and therefore not listed in the register
map tables. SCP0 is a fixed sequence and always starts at the falling edge of
VD. Although this register is not programmable, the CLPEN0 register is still
used to set whether the CLPOB pulse is enabled or disabled for this SCP0
region.
9
1
10
11
4
12
1
5
CLPEN[4:0]
CLPEN0
CLPEN1
CLPEN2
CLPEN3
CLPEN4
B
13
2
14
15
16