AD9929BBCZ Analog Devices Inc, AD9929BBCZ Datasheet - Page 52

• Manufacturer Part Number: AD9929BBCZ
• Description: IC CCD SIGNAL PROCESSOR 64-BGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9929BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9929
STROBE TIMING
The AD9929 provides a STROBE output pulse that can be used
to trigger the camera flash circuit. STROBE operation is set by
only one register, as described in Table 32. The STROBE output
is held low when STROBE_EN (Address 0x0B) is set to 0 and
enabled when set to 1. Providing STROBE_EN = 1, the STROBE
(PIXEL COUNTER)
XSUBCK
H-GRAY CODE
STROBE
XVSG1-
XVSG2
COUNTER
VD
CLI
VD
HD
NOTES
1. STROBE OUTPUT ASSERTED HIGH ON RISING EDGE OF LAST XSUBCK PULSE
2. STROBE OUTPUT ASSERTED LOW ON NEGATIVE EDGE OF XVSG PULSE
NOTES
1. INTERNAL 12-BIT H-GRAY CODE COUNTER IS RESET 7 CLOCK CYCLES AFTER THE HD FALLING EDGE.
X
X
SET STROBE_EN (ADDRESS 0x0B) = 1
X
3ns MIN
Figure 62. External VD/HD and Internal 12-Bit H-Gray Code Counter Synchronization, Slave Mode
X
X
X
X
X
H-COUNTER
RESET
X
0
Figure 61. STROBE Output Timing
1
1
Rev. A | Page 52 of 64
2
3
4
5
output pulse is asserted high on the rising edge of the last
XSUBCK pulse in the field, as shown in Figure 61. Also shown
in Figure 61, the STROBE pulse is asserted low again on the
rising edge of VSG.
6
7
t
8
EXP
9
10
11
12
13
H-COUNTER
RESET
14
0
2
1
2
3
4