AD9929BBCZ Analog Devices Inc, AD9929BBCZ Datasheet
AD9929BBCZ
Specifications of AD9929BBCZ
Available stocks
Related parts for AD9929BBCZ
AD9929BBCZ Summary of contents
Page 1
FEATURES 36 MSPS correlated double sampler (CDS) 12-bit 36 MHz A/D converter On-chip vertical driver for CCD image sensor On-chip horizontal driver for CCD image sensor variable gain amplifier (VGA) Black level clamp with variable ...
Page 2
AD9929 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Specifications ................................................................... 4 Analog Specifications................................................................... 4 Timing Specifications .................................................................. 5 Vertical Driver Specifications ..................................................... 5 Terminology ...................................................................................... 7 Absolute Maximum Ratings............................................................ 8 Pin Configuration and Functional Descriptions.......................... 9 Equivalent Input Circuits .............................................................. 10 ...
Page 3
SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD ( Drivers) DRVDD (Data Output Drivers) DVDD (Digital) VERTICAL DRIVER SUPPLY VOLTAGE VDD (Vertical ...
Page 4
AD9929 DIGITAL SPECIFICATIONS Table 2. RGVDD = HVDD = 2 3.6 V, DVDD = DRVDD = 2 3 Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low ...
Page 5
TIMING SPECIFICATIONS Table pF, AVDD = DVDD = DRVDD = 3 Parameter MASTER CLOCK, CLI CLI Clock Period CLI High/Low Pulse Width Delay from CLI Rising Edge to Internal Pixel Position 0 1 ...
Page 6
AD9929 Parameter V2 and V4 Outputs (See Figure 43) Delay Times VL to VM2 VM2 to VL Rise Times VL to VM2 Fall Times VM2 to VL Output Currents =−7. ...
Page 7
TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. “No missing codes guaranteed to 12-bit resolution” indicates ...
Page 8
AD9929 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter With Respect To VDD VDVSS VL VDVSS VH1, VH2 VDVSS VM1, VM2 VDVSS AVDD AVSS TCVDD TCVSS HVDD HVSS RGVDD RGVSS DVDD DVSS DRVDD DRVSS RG Output RGVSS Output HVSS ...
Page 9
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Table 7. Pin Function Descriptions 1 Pin Mnemonic Type Description Vertical Sync Pulse (Input for Slave D1 VD DIO Mode, Output for Master Mode) Horizontal Sync Pulse (Input for D2 HD DIO Slave Mode, Output ...
Page 10
AD9929 EQUIVALENT INPUT CIRCUITS AVDD R AVSS Figure 3. Circuit 1. CCDIN DVDD DATA THREE- STATE DVSS Figure 4. Circuit 2. Digital Data Output AVSS DRVDD RG, H1 ≠ H2 DOUT ENABLE DRVSS Rev Page ...
Page 11
Table 8. Control Register Address Map Bit Default Address Content Width Value 0x00 (23:0) 24 000000 0x01 (22:21) 2 (20:18 (15:14 (12:10 ...
Page 12
AD9929 Bit Default Address Content Width Value 0x0A (21:16) 6 0x00 (VD (15:12 SyncReg) (11:10 (7: (3: ...
Page 13
Bit Default Address Content Width Value 0x1B (23:13) 11 – (12:0) 13 0x1FFF 0x1C (23:13)) 11 – (12:0 13 0x1FFF 0x1D (23:13) 11 – (12:0) 13 0x1FFF 0x1E (23:13) 11 – (12:0) 13 0x1FFF 0x1F (23:13) 11 – (12:0) 13 ...
Page 14
AD9929 Table 9. System Register Address Map (Address 0x14) Bit Default Register Content Width (Decimal) Sys_Reg(0) (31:24 (23: Sys_Reg(1) (31:23 (18:10) 9 ...
Page 15
Bit Default Register Content Width (Decimal) Sys_Reg(9) (31:23 (18:10 (9: Sys_Reg(10) (31:24 (23:15 (14: ...
Page 16
AD9929 Table 10. Mode_A Register Map (Address 0x15) Bit Register Content Width Mode_Reg(0) (31:24) 8 (23:0) 24 Mode_Reg(1) (31:21) 11 (20: (6:0) 7 Mode_Reg( (30:28) 3 (27:25) 3 (24:22) 3 (21:19) 3 (18:16) ...
Page 17
Table 11. Mode_B Register Map (Address 0x16) Bit Register Content Width Mode_Reg(0) (31:24) 8 (23:0) 24 Mode_Reg(1) (31:21) 11 (20: (6:0) 7 Mode_Reg( (30:28) 3 (27:25) 3 (24:22) 3 (21:19) 3 (18:16) 3 ...
Page 18
AD9929 SYSTEM OVERVIEW Figure 7 shows the typical system block diagram for the AD9929. The CCD output is processed by the AD9929’s AFE circuitry, which consists of a CDS, VGA, black level clamp, and an A/D converter. The digitized pixel ...
Page 19
THEORY OF OPERATION MODES OF OPERATION Slave and Master Mode Operation The AD9929 can be operated in either slave or master mode. It defaults to slave mode operation at power-up. The SLAVE_MODE register (Address 0xD6) can be used to configure ...
Page 20
AD9929 SERIAL INTERFACE TIMING All of the internal registers of the AD9929 are accessed through a 3-wire serial interface. The 3-wire interface consists of a clock (SCK), serial load (SL), and serial data (SDATA). The AD9929 has three different register ...
Page 21
ADDRESS [7:0] SDATA 8 BIT ADDRESS SCK SL NOTES 1. SL PULSES ARE IGNORED UNTIL THE LSB BIT OF THE LAST DATA N WORD IS CLOCKED IN. 2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA ...
Page 22
AD9929 ANALOG FRONT END DESCRIPTION AND OPERATION The AD9929 AFE signal processing chain is shown in Figure 13. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. Registers for the AD9929 AFE ...
Page 23
Variable Gain Amplifier The VGA provides a gain range dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain needed to match input signal with ...
Page 24
AD9929 As shown in Figure 17, the H2 output is the inverse of H1. The internal propagation delay resulting from the signal inversion is less than 1 ns, which is significantly less than the typical rise P[0] POSITION CLI t ...
Page 25
Table 16. Precision Timing Edge Locations for RG, H1, SHP, SHD, DCLK, and DOUTPHASE RG Rising Edge Signal Name Quadrant (Not Programmable fixed at 000000 II fixed at 000000 III fixed at 000000 IV fixed at 000000 Signal ...
Page 26
AD9929 P[0] POSITION PIXEL PERIOD RGr[0] RG Hr[0] H1 CDS (INTERNAL) CCD SIGNAL NOTES 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. 2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. t ...
Page 27
EXTERNAL SYNCHRONIZATION (MASTER MODE) External synchronization can be applied to synchronize the VD and HD signals by applying an external pulse on the SYNC/GATE (Pin 45) pin for master mode operation. The SYNC/GATE pin is configured as an external SYNC ...
Page 28
AD9929 HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING The HD and VD output pulses are programmable using the registers listed in Table 18. The HD output is asserted low at the start of the horizontal line shift. The VD output is asserted ...
Page 29
HORIZONTAL CLAMPING AND BLANKING The AD9929’s horizontal clamping and blanking pulses are programmable to suit a variety of applications. As with the vertical timing generation, individual sequences are defined for each signal, which are then organized into multiple regions during ...
Page 30
AD9929 VD HD 12-BIT GRAY COUNTER + SET-UP CLPOB PROGRAMMABLE CLOCK POSITIONS 1. CLPTOG1 (SYS_REG (15)) 2. CLPTOG2 (SYS_REG (15 AND 16 CLPOB CLPMASK (INTERNAL PROGRAMMING POSITIONS 1. SCP0 = 0 (FIXED), CLPEN0 ...
Page 31
H1 AND H2 BLANKING The AD9929 provides three options for controlling the period where H1 and H2 pulses get blanked. These options are normal H blanking, selective positioning for 2 H1 and H2 outputs, and extended blanking. In all cases, ...
Page 32
AD9929 HD HBLK (INTERNAL) H12 (INTERNAL NOTES THE OPPOSITE POLARITY OF H1 Figure 28. Selective H-Blanking Operation HBLKMASK = 0, HPULSECNT = 1, HBLKHPOS = 003. BLLEN 9-BIT BL COUNTER CLPOB NOTES ...
Page 33
VGATE MASKING OF XV1 TO XV4 AND CLPOB OUTPUTS During slave mode operation, the SYNC/VGATE Pin 45 is configured as an input for an external VGATE signal. While operating in this mode, the external VGATE signal can be used to ...
Page 34
AD9929 VERTICAL TIMING GENERATION The AD9929 provides a very flexible solution for generating vertical CCD timing and can support multiple CCDs and different system architectures. The 4-phase vertical transfer clocks XV1 to XV4 are used to shift each line of ...
Page 35
HD XV1 XV2 7 8 XV3 XV4 10 11 VTPLENx [8:0] = 210 1. XV1STARTPOLx = 0 2. XV1TOG1x [8: XV2STARTPOLx = 1 5. XV2TOG1x [8: XV3STARTPOLx ...
Page 36
AD9929 VERTICAL TRANSFER PULSES { { XV1 XV1 XV2 XV2 VTP0 VTP1 XV3 XV3 XV4 XV4 { { XV1 XV1 XV2 XV2 VTP2 VTP3 XV3 XV3 XV4 XV4 SCP 0 REGION 0 (FIXED AT LINE XV1 XV2 ...
Page 37
Table 22. XV1 to XV4 Registers to Configure XXV1 to XXV4 Pulses for each VTP Pattern Bit Register Name Width Register Type VTPLEN0 9 Sys_Reg(1) XV1STARTPOL0 1 Sys_Reg(1) XV2STARTPOL0 1 Sys_Reg(1) XV3STARTPOL0 1 Sys_Reg(1) XV4STARTPOL0 1 Sys_Reg(1) XV1TOG1POS0 9 Sys_Reg(1) ...
Page 38
AD9929 Bit Register Name Width Register Type VTPLEN3 9 Sys_Reg(9) XV1STARTPOL3 1 Sys_Reg(9) XV2STARTPOL3 1 Sys_Reg(9) XV3STARTPOL3 1 Sys_Reg(9) XV4STARTPOL3 1 Sys_Reg(9) XV1TOG1POS3 9 Sys_Reg(9) XV1TOG2POS3 9 Sys_Reg(9) XV2TOG1POS3 9 Sys_Reg(9 &10) XV2TOG2POS3 9 Sys_Reg(10) XV3TOG1POS3 9 Sys_Reg(10) XV3TOG2POS3 9 ...
Page 39
SPECIAL VERTICAL SWEEP MODE OPERATION The AD9929 contains a special mode of vertical timing oper- ation called sweep mode. This mode is used to generate a continuous number of repetitive vertical pulses that span multiple HD lines. One example of ...
Page 40
AD9929 SPECIAL VERTICAL TIMING (SPATS) The AD9929 provides additional special vertical timing gen- eration (SPATs), which is applied in the same line as the VSG pulse. The SPAT timing allows for an additional vertical output pulse in the VSG line. ...
Page 41
Bit Register Name Width Register Type XV2SPAT_TOG1 13 Control (Address 0x21) XV2SPAT_TOG2 13 Control (Address 0x22) XV2SPAT_TOG3 13 Mode_B_Reg(5) XV2SPAT_TOG4 13 Mode_B_Reg(5) XV3SPAT_TOG1 13 Control (Address 0x23) XV3SPAT_TOG2 13 Control (Address 0x24) XV3SPAT_TOG3 13 Mode_B_Reg(5) XV3SPAT_TOG4 13 Mode_B_Reg(5) XV4SPAT_TOG1 13 ...
Page 42
AD9929 VD HD 13-BIT ST COUNTER (FIXED) INTERNAL XV2 WITHOUT SPAT APPLIED INTERNAL SPAT TIMING FOR XV2 WITH SPATLOGIC = 1 XV2 OUTPUT WITH SPAT APPLIED XVSGx NOTES 1. THE XVxSPAT_TOG1 AND XVxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER. 2. ...
Page 43
AND SUBCK OUTPUT POLARITIES As shown in Figure 41, the XV1 to XV4 and XSUBCK are output signals from the AD9929 timing generator, whereas the and SUBCK are output signals from the AD9929 vertical ...
Page 44
AD9929 XV2 XV4 V2 V4 XSUBCK SUBCK XV1 XVSG1 VH1 V1 VM1 VL XV3 XVSG2 VH1 V3 VM1 VL 50% t PML2 90% 10 Figure 43. V2 and V4 Transmission Delays and Rise Times 50% t PLH 90% ...
Page 45
XV2 XV4 VM2 Figure 47. Example Showing V2 and V4 Outputs versus XV2 and XV4 Signals XSUBCK VH2 SUBCK VL Figure 48. Example Showing SUBCK Output versus XSUBCK Signal Rev Page AD9929 ...
Page 46
AD9929 TIMING CONTROL ELECTRONIC SHUTTER TIMING CONTROL CCD image exposure time is controlled through the use of the CCD substrate clock signal (XSUBCK), which pulses the CCD substrate to clear out accumulated charges prior to the exposure period. The AD9929 ...
Page 47
VD HD XVSG1- XVSG2 XSUBCK SUBCK PROGRAMMABLE SETTINGS 1. XSUBCK STARTING POLARITY IS ALWAYS HIGH. 2. FALLING EDGE OF XSUBCK IS SET USING THE XSUBCK1TOG1 OR XSUBCK2TOG1 REGISTERS. 3. RISING EDGE OF XSUBCK IS SET USING THE ...
Page 48
AD9929 VSG TIMING The VSG Timing is controlled using the registers in Table 35. Two unique preprogrammed VSG pulses can be configured using the XVSGTOG_x ( registers. As shown in Figure 55, the period of the VSG ...
Page 49
13-BIT ST COUNTER (FIXED) XVSGTOG_0 XVSGTOG_1 NOTES 1. XVSGTOG_x ( REFERENCES THE 13-BIT ST COUNTER 2. XVSGACTLINE (PROGRAMMABLE AT MODE_REG(1)) 3. XVSGLEN (PROGRAMMABLE AT SYS_REG(14)) PROGRAMMABLE CLOCK POSITIONS 1. XVSGTOG_0 (PROGRAMMABLE AT SYS_REG(13)) 2. ...
Page 50
AD9929 MSHUT TIMING MSHUT Basic Operation The AD9929 provides an MSHUT output pulse that can be con- figured to control the mechanical shutter of the camera. The registers used to control the MSHUT pulse are listed in Table 37. The ...
Page 51
MSHUT High Precision Operation The MSHUTPOS_HP register allows fine precision control of the MSHUT position within a line. Under normal MSHUT operation when MSHUTPOS_HP = 0, the MSHUT polarity changes from high to low on the negative edge of the ...
Page 52
AD9929 STROBE TIMING The AD9929 provides a STROBE output pulse that can be used to trigger the camera flash circuit. STROBE operation is set by only one register, as described in Table 32. The STROBE output is held low when ...
Page 53
DIGITAL I/O STATES FOR DIFFERENT OPERATING CONDITIONS Table 38 describes the state of the digital I/Os for different operating conditions. Table 38. I/O Levels 1 I/O OCONT_REG = 0 DIGSTBY DCLK1 ACTIVE H DCLK2 ACTIVE ACTIVE ...
Page 54
AD9929 POWER SUPPLY SEQUENCING The recommended power-up and power-down sequences are shown in Figure 64 and Figure 65, respectively. As shown, the VM1 and VM2 voltage level should never exceed the VH1 and VH2 voltage level during power-up or power-down. ...
Page 55
INITIAL START-UP SEQUENCE Recommended Start-Up Sequence for Master Mode When the AD9929 is powered up, the following sequence is recommended (refer to Figure 66 for each step). 1. Turn on power supplies as described in the Power Supply Sequencing section. ...
Page 56
AD9929 STANDBY MODE OPERATION Recommended Standby Mode Sequence When the AD9929 is going into standby operation, the follow- ing sequence is recommended (refer to Figure 67 for each step). 1. Program OUTCONT_REG (Address 0x05 This asserts the internal ...
Page 57
SHUT-DOWN MODE OPERATION Recommended Power-Down Sequence When the AD9929 is going to be powered down, the following sequence is recommended (refer to Figure 68 for each step). VDD (INPUT) CLI (INPUT) OUTCONT (INTERNAL) SERIAL WRITES VD ODD FIELD (OUTPUT) HD ...
Page 58
AD9929 APPLICATIONS WHERE THE CLI CLOCK FREQUENCY CHANGES DURING OPERATION The AD9929 must be reset, as described in Figure 69, if the CLI clock frequency is changed during operation. The DCLK1 FAST CL SERIAL WRITES OUTCONT (INTERNAL SIGNAL) VD (OUTPUT) ...
Page 59
CCD SIGNAL SHP t S1 SHD CYCLE 1 CYCLE 2 CYCLE 3 CLI VCLIDLY OUTPUT N – – – ...
Page 60
AD9929 CIRCUIT LAYOUT INFORMATION The AD9929 typical circuit connection is shown in Figure 71. The PCB layout is critical in achieving good image quality from the AD9929 product. All of the supply pins must be decoupled to ground with good ...
Page 61
DRIVER SUPPLY 12 DATA OUTPUTS DCLK1 TO MECHANICAL MSHUT SHUTTER CIRCUIT STROBE TO STROBE CIRCUIT FD/DCLK2 FD/DCLK2 ASIC/DSP ASIC/DSP HVDD 3V ANALOG SUPPLY HVSS 0.1 µ F HVSS HVSS H1, ...
Page 62
... AD9929 OUTLINE DIMENSIONS 1.00 0.85 1.40 MAX ORDERING GUIDE Model Temperature Range 1 AD9929BBCZ −25°C to +85° Pb-free part. 9.00 BSC BALL A1 INDICATOR BOTTOM TOP VIEW 0.90 REF SQ 7.20 BSC DETAIL A 0.25 MIN 0.80 BSC BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-205-AB Figure 72 ...
Page 63
NOTES Rev Page AD9929 ...
Page 64
AD9929 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04593-0-1/04(A) Rev Page ...