ST92T163R4T1 STMicroelectronics, ST92T163R4T1 Datasheet - Page 71

• Manufacturer Part Number: ST92T163R4T1
• Description: Microcontrollers (MCU) OTP EPROM 20K USB/I2
• Manufacturer: STMicroelectronics

Specifications of ST92T163R4T1

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 20 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

4.3 DMA TRANSACTIONS
The purpose of an on-chip DMA channel is to
transfer a block of data between a peripheral and
the Register File, or Memory. Each DMA transfer
consists of three operations:
– A load from/to the peripheral data register to/
– A post-increment of the DMA Address Register
– A post-decrement of the DMA transaction coun-
If the DMA transaction is carried out between the
peripheral and the Register File (Figure 32), one
register is required to hold the DMA Address, and
one to hold the DMA transaction counter. These
two registers must be located in the Register File:
the DMA Address Register in the even address
Figure 32. DMA Between Register File and Peripheral
from a location of Register File (or Memory) ad-
dressed through the DMA Address Register (or
Register pair)
(or Register pair)
ter, which contains the number of transactions
that have still to be performed.
PAGED REGISTERS
PERIPHERAL
DAPR
DCPR
DATA
IDCR
IVR
TABLE
DMA
FFh
F0h
EFh
E0h
DFh
TRANSFERRED
REGISTER FILE
ST92163 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
REGISTERS
REGISTERS
COUNTER
ADDRESS
ALREADY
SYSTEM
PAGED
DMA
DATA
DMA
register, and the DMA Transaction Counter in the
next register (odd address). They are pointed to by
the DMA Transaction Counter Pointer Register
(DCPR), located in the peripheral’s paged regis-
ters. In order to select a DMA transaction with the
Register File, the control bit DCPR.RM (bit 0 of
DCPR) must be set.
If the transaction is made between the peripheral
and Memory, a register pair (16 bits) is required
for the DMA Address and the DMA Transaction
Counter (Figure 33). Thus, two register pairs must
be located in the Register File.
The DMA Transaction Counter is pointed to by the
DMA Transaction Counter
(DCPR), the DMA Address is pointed to by the
DMA Address Pointer Register (DAPR),both
DCPR and DAPR are located in the paged regis-
ters of the peripheral.
0000h
0100h
SERVICE ROUTINE
END OF BLOCK
ISR ADDRESS
INTERRUPT
MEMORY
Pointer Register
VECTOR
TABLE
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