ST92T163R4T1 STMicroelectronics, ST92T163R4T1 Datasheet - Page 150

• Manufacturer Part Number: ST92T163R4T1
• Description: Microcontrollers (MCU) OTP EPROM 20K USB/I2
• Manufacturer: STMicroelectronics

Specifications of ST92T163R4T1

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 20 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST92163 - SERIAL COMMUNICATIONS INTERFACE (SCI)
8.4 SERIAL COMMUNICATIONS INTERFACE (SCI)
8.4.1 Introduction
The Serial Communications Interface (SCI) offers
full-duplex serial data exchange with a wide range
of external equipment. The SCI offers four operat-
ing modes: Asynchronous, Asynchronous with
synchronous clock, Serial expansion and Syn-
chronous.
The SCI offers the following principal features:
Figure 71. SCI Block Diagram
150/224
Full duplex synchronous and asynchronous
operation.
Transmit, receive, line status, and device
address interrupt generation.
Integral Baud Rate Generator capable of
dividing the input clock by any value from 2 to
2
16X data sampling clock for asynchronous
operation or the 1X clock for synchronous
operation.
Fully programmable serial interface:
– 5, 6, 7, or 8 bit word length.
– Even, odd, or no parity generation and detec-
– 0, 1, 1.5, 2, 2.5, 3 stop bit generation.
– Complete status reporting capabilities.
– Line break generation and detection.
16
tion.
-1 (16 bit word) and generating the internal
SOUT
TRANSMIT
REGISTER
TRANSMIT
REGISTER
BUFFER
SHIFT
RTS
CONTROLLER
SDS
DMA
TXCLK/CLKOUT RXCLK
ST9 CORE BUS
Frame Control
ALTERNATE
COMPARE
ADDRESS
REGISTER
and STATUS
FUNCTION
CLOCK and
BAUD RATE
GENERATOR
CONTROLLER
DMA
– Local loopback for communications link fault
– Auto-echo for communications link fault isola-
– High speed communication
– Possibility of hardware synchronization (RTS/
– Programmable polarity and stand-by level for
– Programmable active edge and stand-by level
– Programmable active levels of RTS/DCD sig-
– Full Loop-Back and Auto-Echo modes for DA-
Programmable address indication bit (wake-up
bit) and user invisible compare logic to support
multiple microcomputer networking. Optional
character search function.
Internal diagnostic capabilities:
Separate interrupt/DMA channels for transmit
and receive.
In addition, a Synchronous mode supports:
DCD
RECEIVER
REGISTER
RECEIVER
REGISTER
BUFFER
isolation.
tion.
DCD signals).
data SIN/SOUT.
for clocks CLKOUT/RXCL.
nals.
TA, CLOCKs and CONTROLs.
SHIFT
SIN
VA00169A