ST92T163R4T1 STMicroelectronics, ST92T163R4T1 Datasheet - Page 148

Microcontrollers (MCU) OTP EPROM 20K USB/I2

ST92T163R4T1

Manufacturer Part Number
ST92T163R4T1
Description
Microcontrollers (MCU) OTP EPROM 20K USB/I2
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST92T163R4T1

Data Bus Width
8 bit, 16 bit
Program Memory Type
EPROM
Program Memory Size
20 KB
Data Ram Size
2 KB
Interface Type
I2C, SCI, USB
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
64
Number Of Timers
2
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
TQFP-64
Minimum Operating Temperature
0 C
On-chip Adc
8 bit
Lead Free Status / Rohs Status
No

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ST92163 - USB PERIPHERAL (USB)
USB INTERFACE (Cont’d)
8.3.5 Register pages summary
The registers are located in different register file
pages. To help finding the correct page for each
Table 29. USB Register Page Mapping
Table 30. USB Register page 15 Map and Reset Values
148/224
Reg.
R240
R247
R248
R249
R250
R251
R252
No.
-
250 (FAh)
251 (FBh)
252 (FCh)
253 (FDh)
254 (FEh)
240 (F0h)
241 (F1h)
242 (F2h)
243 (F3h)
244 (F4h)
245 (F5h)
246 (F6h)
247 (F7h)
248 (F8h)
249 (F9h)
255 (FFh)
Address
DADDRn
Reset Value
USBIVR
Reset Value
USBISTR
Reset Value
USBIMR
Reset Value
USBIPR
Reset Value
USBCTLR
Reset Value
Register
Name
IEE
EF
A1
7
0
0
0
0
0
0
0
0
x
EP0RA
EP0RB
EP1RA
EP1RB
EP2RA
EP2RB
EP3RA
EP3RB
EP4RA
EP4RB
EP5RA
EP5RB
EP6RA
EP6RB
EP7RA
EP7RB
Page 4
TIM_SUSP
DOVRM
PIECE2
DOVR
ADD6
A0
6
0
0
0
0
x
x
DOVRM
PIECE1
DOVR
CTRO
ADD5
5
0
x
0
0
x
0
0
EP10RA
EP10RB
EP11RA
EP11RB
EP12RA
EP12RB
EP13RA
EP13RB
EP14RA
EP14RB
EP15RA
EP15RB
Page 5
EP8RA
EP8RB
EP9RA
EP9RB
register, the following tables show the page map-
ping of all USB registers.
ESUSPM
PIECE0
SDNAV
ESUSP
ADD4
V3
4
0
x
0
0
x
1
RESUME
SUSPM
ADD3
SUSP
NIEE
V2
USBCTLR
3
0
x
0
0
0
0
USBISTR
DADDR0
DADDR1
DADDR2
DADDR3
DADDR4
DADDR5
DADDR6
DADDR7
Page 15
USBIMR
USBIVR
USBIPR
CTRINF
FNRH
FNRL
RESETM
PNIEN2
PDWN
RESET
ADD2
V1
2
0
x
0
0
x
1
LP_SUSP
PNIEN1
SOFM
ADD1
SOF
V0
DEVCONF1
DEVCONF2
1
0
x
0
0
x
0
Page 60
MIRRA
MIRRB
PNIEN0
ESOFM
FRES
ESOF
ADD0
0
0
0
0
0
x
1
0

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