ST92T163R4T1 STMicroelectronics, ST92T163R4T1 Datasheet - Page 143

• Manufacturer Part Number: ST92T163R4T1
• Description: Microcontrollers (MCU) OTP EPROM 20K USB/I2
• Manufacturer: STMicroelectronics

Specifications of ST92T163R4T1

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: EPROM
• Program Memory Size: 20 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, USB
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

USB INTERFACE (Cont’d)
DEVICE n ADDRESS (DADDRn)
R240 to R247 - Read/Write
Register page: 15
Reset Value: 0000 0000 (00h)
Note: This register is also reset when a USB reset
is received from the USB bus or forced through bit
FRES in the USBCTLR register.
Bit 7 = EF: Enable Function .
Set by software to enable the USB function whose
address is contained in the following ADD[6:0]
bits.
0: Function disabled
1: Function enabled
Bits 6:0 = ADD[6:0]: Device Address .
Software must write into these bits the USB device
address assigned by the host PC during the enu-
meration.
ENDPOINT n REGISTER A (EPnRA)
(TRANSMISSION)
R240-R254 (even)
Read/Write
Register pages: 4 & 5
Reset value: 0000 0000 (00h)
These registers are used for controlling data trans-
mission. They are also reset when a USB reset is
received or forced through the FRES bit in the US-
BCTLR register.
Note: The CTR bits are not affected by a USB re-
set
CTR
EF
7
7
DTOG_
ADD6 ADD5 ADD4
TX
STAT_
TX1
STAT_
TX0
ADD3 ADD2 ADD1 ADD0
PIDR1 PIDR0
CEP
ISO
0
0
Each endpoint has its EPnRA register where n is
the endpoint identifier in the range 0 to 15.
Bit 7 = CTR: Correct Transfer .
Set by hardware when a transaction is successful-
ly completed on this endpoint; software can only
clear this bit.
0: No correct transfer occured
1: Correct transfer occured
Note: A transaction ended with a NAK or STALL
handshake does not set this bit, since no data is
actually transferred, as in the case of protocol er-
rors or data toggle mismatches. The CTR bit is
also used to perform flow control: while CTR=1, a
valid endpoint answers NAK to every transaction
addressed to it (except SETUP requests which are
simply ignored) until the application software ac-
knowledges the CTR event, resetting this bit. This
does not apply to isochronous endpoints where no
handshake phase is used.
Bit 6 = DTOG_TX: Data Toggle, for transmission
transfers .
If the endpoint is non-isochronous, this bit contains
the required value of the data toggle bit
(0=DATA0, 1=DATA1) for the next data packet to
be transmitted. Hardware toggles this bit when the
ACK handshake is received from the USB host,
following a data packet transmission. If the end-
point is defined as a control one, hardware sets
this bit to 1 on reception of a SETUP PID ad-
dressed to this endpoint.
If the endpoint is isochronous, this bit is used to
support DMA buffer swapping since no data tog-
gling is used for this sort of endpoint and only
DATA0 packet are transmitted. Hardware toggles
this bit just after the end of data packet transmis-
sion, since no handshake is used for isochronous
transfers.
Note: this bit can be also written by software to in-
itialize it (mandatory when the endpoint is not a
control endpoint) or to force specific data toggle/
DMA buffer usage.
ST92163 - USB PERIPHERAL (USB)
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