PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 67

• Manufacturer Part Number: PIC18F46K80-I/P
• Description: 40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/P

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

4.0
The PIC18F66K80 family of devices offers a total of
seven operating modes for more efficient power man-
agement. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (such as battery-powered
devices).
There are three categories of power-managed mode:
• Run modes
• Idle modes
• Sleep mode
There is an Ultra Low-Power Wake-up (ULPWU) for
waking from Sleep mode.
These categories define which portions of the device
are clocked, and sometimes, at what speed. The Run
and Idle modes may use any of the three available
clock sources (primary, secondary or internal oscillator
block). The Sleep mode does not use a clock source.
The ULPWU mode, on the RA0 pin, enables a slow fall-
ing voltage to generate a wake-up, even from Sleep,
without excess current consumption. (See
“Ultra Low-Power
The power-managed modes include several power-
saving features offered on previous PIC
is the clock switching feature, offered in other PIC18
devices. This feature allows the controller to use the
SOSC oscillator instead of the primary one. Another
power-saving feature is Sleep mode, offered by all PIC
devices, where all device clocks are stopped.
4.1
Selecting a power-managed mode requires two
decisions:
• Will the CPU be clocked or not
• What will be the clock source
TABLE 4-1:
 2011 Microchip Technology Inc.
Sleep
PRI_RUN
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
Note 1:
Mode
2:
POWER-MANAGED MODES
Selecting Power-Managed Modes
IDLEN reflects its value when the SLEEP instruction is executed.
Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC
source.
IDLEN<7>
POWER-MANAGED MODES
N/A
N/A
N/A
Wake-up”.)
0
1
1
1
OSCCON Bits
(1)
SCS<1:0>
N/A
00
01
1x
00
01
1x
®
devices. One
Section 4.7
Clocked
Clocked
Clocked
CPU
Module Clocking
Off
Off
Off
Off
Preliminary
Peripherals
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
PIC18F66K80 FAMILY
Off
The IDLEN bit (OSCCON<7>) controls CPU clocking,
while the SCS<1:0> bits (OSCCON<1:0>) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table
4.1.1
The SCS<1:0> bits select one of three clock sources
for power-managed modes. Those sources are:
• The primary clock as defined by the FOSC<3:0>
• The secondary clock (the SOSC oscillator)
• The internal oscillator block (for LF-INTOSC
4.1.2
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is used. Changing these bits
causes an immediate switch to the new clock source,
assuming that it is running. The switch may also be
subject to clock transition delays. These considerations
are discussed in
and Status Indicators”
Entering the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current and impending mode, a
change to a power-managed mode does not always
require setting all of the previously discussed bits. Many
transitions can be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured as
desired, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
Configuration bits
modes)
4-1.
None – All clocks are disabled
Primary – XT, LP, HS, EC, RC and PLL modes.
This is the normal, full-power execution mode.
Secondary – SOSC Oscillator
Internal oscillator block
Primary – LP, XT, HS, RC, EC
Secondary – SOSC oscillator
Internal oscillator block
Available Clock and Oscillator Source
CLOCK SOURCES
ENTERING POWER-MANAGED
MODES
Section 4.1.3 “Clock Transitions
and subsequent sections.
(2)
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DS39977C-page 67