PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 193

• Manufacturer Part Number: PIC18F46K80-I/P
• Description: 40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/P

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

11.6
PORTE is a seven-bit-wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISE and LATE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PADCFG1<6>). The
TABLE 11-9:
 2011 Microchip Technology Inc.
RE0/AN5/RD
RE1/AN6/
C1OUT/WR
RE2/AN7/
C2OUT/CS
RE3
RE4/CANRX
Legend:
Note 1:
Note:
Note:
Pin Name
2:
PORTE, TRISE and
LATE Registers
O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Unavailable for 40 and 44-pin devices (PIC18F4XK0).
Alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX Configuration
bit is cleared.
PORTE is unavailable on 28-pin devices.
These pins are configured as digital inputs
on any device Reset.
CANRX
Function
PORTE FUNCTIONS
C1OUT
C2OUT
RE4
RE0
AN5
RE1
AN6
RE2
AN7
RE3
WR
RD
CS
(1)
(1,2)
Setting
TRIS
0
1
1
x
x
0
1
1
0
x
x
0
1
1
0
x
1
0
1
1
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I/O Type
ANA
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATE<0> data output.
PORTE<0> data input.
A/D Input Channel 5. Default input configuration on POR; does not
affect digital output.
Parallel Slave Port read strobe pin.
Parallel Slave Port read pin.
LATE<1> data output.
PORTE<1> data input.
A/D Input Channel 5. Default input configuration on POR; does not
affect digital output.
Comparator 1 output; takes priority over port data.
Parallel Slave Port write strobe pin.
Parallel Slave Port write pin.
LATE<2> data output.
PORTE<2> data input.
A/D Input Channel 7. Default input configuration on POR; does not
affect digital output.
Comparator 2 output; takes priority over port data.
Parallel Slave Port chip select.
PORT<3> data input.
LATE<4> data output.
PORTE<4> data input.
CAN bus RX.
PIC18F66K80 FAMILY
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
PORTE is also multiplexed with the Parallel Slave Port
address lines. RE1 and RE0 are multiplexed with the
Parallel Slave Port (PSP) control signals, WR and RD.
EXAMPLE 11-5:
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
03h
TRISE
Description
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
INITIALIZING PORTE
DS39977C-page 193