PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 579
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F46K80-I/P
Manufacturer Part Number
PIC18F46K80-I/P
Description
40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F46K80-I/P
A/d Inputs
11-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
1K Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PDIP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
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Quantity
Price
Company:
Part Number:
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Manufacturer:
BROADCOM
Quantity:
101
Company:
Part Number:
PIC18F46K80-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F46K80-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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FIGURE 31-12:
TABLE 31-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
2011 Microchip Technology Inc.
73
73A
74
75
76
78
79
80
81
Param.
No.
Note:
SCKx
(CKPx = 0 )
SCKx
(CKPx = 1 )
SDOx
SDIx
T
T
T
T
T
T
T
T
T
T
T
T
T
SC
SC
SC
SC
SC
SC
DI
DI
B
DO
DO
DO
DO
Symbol
2
Refer to
V2
V2
H2
L2
R
F
H2
L2
B
R
F
V2
V2
SC
SC
DI
DO
DI
DO
SC
SC
L
L,
H,
L
V
V,
H,
L
Figure 31-3
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
Setup Time of SDIx Data Input to SCKx Edge
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
Hold Time of SDIx Data Input to SCKx Edge
SDOx Data Output Rise Time
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
SDOx Data Output Valid after SCKx Edge
SDOx Data Output Setup to SCKx Edge
81
73
MSb In
MSb
for load conditions.
74
75, 76
Characteristic
80
bit 6 - - - - - - 1
bit 6 - - - - 1
Preliminary
PIC18F66K80 FAMILY
LSb In
LSb
1.5 T
Min
T
CY
20
40
79
78
—
—
—
—
—
CY
+ 40
Max Units
25
25
25
25
50
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS39977C-page 579
Conditions
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