PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 180

• Manufacturer Part Number: PIC18F46K80-I/P
• Description: 40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/P

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
11.1.4
Many of the ports multiplex analog and digital function-
ality, providing a lot of flexibility for hardware designers.
PIC18F66K80 family devices can make any analog pin
analog or digital, depending on an application’s needs.
The ports’ analog/digital functionality is controlled by
the registers: ANCON0 and ANCON1.
Setting these registers makes the corresponding pins
analog and clearing the registers makes the ports digi-
tal. For details on these registers, see
“12-Bit Analog-to-Digital Converter (A/D) Module”
REGISTER 11-4:
DS39977C-page 180
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
2:
Unimplemented and read back as ‘ 0 ’ on 28-pin and 40/44-pin devices.
Unimplemented and read back as ‘ 0 ’ on 28-pin devices.
ANALOG AND DIGITAL PORTS
Unimplemented: Read as ‘ 0 ’
SLRG: PORTG Slew Rate Control bit
1 = All output pins on PORTG slew at 0.1 the standard rate
0 = All output pins on PORTG slew at standard rate
SLRF: PORTF Slew Rate Control bit
1 = All output pins on PORTF slew at 0.1 the standard rate
0 = RAll output pins on PORTF slew at standard rate
SLRE: PORTE Slew Rate Control bit
1 = All output pins on PORTE slew at 0.1 the standard rate
0 = All output pins on PORTE slew at standard rate
SLRD: PORTD Slew Rate Control bit
1 = All output pins on PORTD slew at 0.1 the standard rate
0 = All output pins on PORTD slew at standard rate
SLRC: PORTC Slew Rate Control bit
1 = All output pins on PORTC slew at 0.1 the standard rate
0 = All output pins on PORTC slew at standard rate
SLRB: PORTB Slew Rate Control bit
1 = All output pins on PORTB slew at 0.1 the standard rate
0 = All output pins on PORTB slew at standard rate
SLRA: PORTA Slew Rate Control bit
1 = All output pins on PORTA slew at 0.1 the standard rate
0 = All output pins on PORTA slew at standard rate
SLRG
R/W-0
SLRCON: SLEW RATE CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
SLRF
R/W-0
(1)
Section 23.0
SLRE
R/W-0
Preliminary
(1)
(2)
(2)
(2)
(2)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SLRD
R/W-0
11.1.5
The output slew rate of each port is programmable to
select either the standard transition rate, or a reduced
transition rate of ten percent of the standard transition
time, to minimize EMI. The reduced transition time is
the default slew rate for all ports.
(2)
PORT SLEW RATE
SLRC
R/W-0
(2)
 2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
SLRB
R/W-0
SLRA
bit 0