PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 450

• Manufacturer Part Number: PIC18F46K80-I/P
• Description: 40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/P

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

prescaler and number of time quanta in each segment.
nominal bit rate is defined to be a maximum of 1 Mb/s.
PIC18F66K80 FAMILY
27.9
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non-Return-
to-Zero (NRZ) coding which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitter’s clock.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the PIC18F66K80 family is imple-
mented using a DPLL that is configured to synchronize
to the incoming data and provides the nominal timing
for the transmitted data. The DPLL breaks each bit time
into multiple segments made up of minimal periods of
time called the Time Quanta (T
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different clock
frequencies of the individual devices, the bit rate has to
be adjusted by appropriately setting the baud rate
The “Nominal Bit Rate” is the number of bits transmitted
per second, assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
The “Nominal Bit Time” is defined as:
EQUATION 27-1:
FIGURE 27-4:
DS39977C-page 450
Input
Signal
Bit
Time
Intervals
T
Baud Rate Setting
Q
T
BIT
= 1/Nominal Bit Rate
Segment
BIT TIME PARTITIONING
Sync
Sync
Q
Propagation
).
Segment
Preliminary
Segment 1
Phase
Nominal Bit Time
The Nominal Bit Time can be thought of as being
divided into separate, non-overlapping time segments.
These segments
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 (Phase_Seg2)
The time segments (and thus, the Nominal Bit Time)
are, in turn, made up of integer units of time called Time
Quanta or T
Nominal Bit Time is programmable from a minimum of
8 T
minimum Nominal Bit Time is 1  s, corresponding to a
maximum 1 Mb/s rate. The actual duration is given by
the following relationship.
EQUATION 27-2:
The Time Quantum is a fixed unit derived from the
oscillator period. It is also defined by the programmable
baud rate prescaler, with integer values from 1 to 64, in
addition to a fixed divide-by-two for clock generation.
Mathematically, this is:
EQUATION 27-3:
where F
corresponding oscillator period and BRP is an integer
(0 through 63) represented by the binary values of
BRGCON1<5:0>. The equation above refers to the
effective clock frequency used by the microcontroller. If,
for example, a 10 MHz crystal in HS mode is used, then
F
crystal is used in HS-PLL mode, then the effective
frequency is F
OSC
Q
Nominal Bit Time = T
to a maximum of 25 T
= 10 MHz and T
Sample Point
OSC
T
T
Q
Q
(s) = (2 * (BRP + 1))/F
(s) = (2 * (BRP + 1)) * T
Q
OSC
Phase_Seg1 + Phase_Seg2)
is the clock frequency, T
(see
(Figure
= 40 MHz and T
OSC
Figure
 2011 Microchip Technology Inc.
Q
Segment 2
27-4) include:
= 100 ns. If the same 10 MHz
* (Sync_Seg + Prop_Seg +
or
Phase
27-4). By definition, the
Q
. Also by definition, the
OSC
OSC
OSC
(MHz)
= 25 ns.
(s)
OSC
is the