PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 375

• Manufacturer Part Number: PIC18F46K80-I/P
• Description: 40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/P

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

23.8
A/D conversion can be started by the Special Event
Trigger of any of these modules:
• CCP2 – Requires CCP2M<3:0> bits
• ECCP1
• CTMU – Requires the setting of the CTTRIG bit
• Timer1
To start an A/D conversion:
• The A/D module must be enabled (ADON = 1 )
• The appropriate analog input channel selected
• The minimum acquisition period set one of these
With these conditions met, the trigger sets the
GO/DONE bit and the A/D acquisition starts.
If the A/D module is not enabled (ADON = 0 ), the
module ignores the Special Event Trigger.
 2011 Microchip Technology Inc.
(CCP2CON<3:0>) set at ‘ 1011 ’
(CTMUCONH<0>)
ways:
- Timing provided by the user
- Selection made of an appropriate T
Note:
Use of the Special Event Triggers
With an ECCP1 or CCP2 trigger, Timer1
or Timer3 is cleared. The timers reset to
automatically repeat the A/D acquisition
period with minimal software overhead
(moving ADRESH:ADRESL to the desired
location). If the A/D module is not enabled,
the Special Event Trigger is ignored by the
module, but the timer’s counter resets.
(†)
ACQ
time
Preliminary
PIC18F66K80 FAMILY
23.9
The selection of the automatic acquisition time and A/D
conversion clock is determined, in part, by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used.
After the power-managed mode is entered (either of the
power-managed Run modes), an A/D acquisition or
conversion may be started. Once an acquisition or con-
version is started, the device should continue to be
clocked by the same power-managed mode clock source
until the conversion has been completed. If desired, the
device
power-managed Idle mode during the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires that the A/D RC
clock be selected. If bits, ACQT<2:0>, are set to ‘ 000 ’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry into Sleep mode. The
IDLEN and SCS<1:0> bits in the OSCCON register
must have already been cleared prior to starting the
conversion.
may
Operation in Power-Managed
Modes
be
placed
into the
DS39977C-page 375
corresponding