PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 188

• Manufacturer Part Number: PIC18F46K80-I/P
• Description: 40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/P

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
TABLE 11-5:
DS39977C-page 188
RC0/SOSCO/
SCLKI
RC1/SOSCI
RC2/T1G/
CCP2
RC3/REFO/
SCL/SCK
RC4/SDA/SDI
RC5/SDO
RC6/CANTX/
TX1/CK1/
CCP3
Legend:
Note 1:
Pin Name
2:
O = Output, I = Input, I
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Pin assignment for 28, 40 and 44-pin devices (PIC18F2XK80 and PIC18F4XK80).
Alternate pin assignment for CANRX and CANTX on 28, 40 and 44-pin devices (PIC18F4XK80) when the CANMX
Configuration bit is set.
CANTX
Function
SOSCO
SOSCI
SCLKI
CK1
REFO
TX1
CCP2
CCP3
SDO
RC0
RC1
RC2
T1G
RC3
SCL
SCK
RC4
SDA
RC5
RC6
PORTC FUNCTIONS
SDI
(1)
(1)
(1)
Setting
TRIS
0
1
1
1
0
1
x
0
1
x
0
1
0
1
x
0
1
0
1
0
1
1
1
1
0
1
0
0
1
0
0
0
1
0
1
2
C = I
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
C/SMBus, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
Type
ANA SOSC oscillator input.
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I
I
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
2
2
C
C
I
I
LATC<0> data output.
PORTC<0> data input.
SOSC oscillator output.
Digital clock input; enabled when SOSC oscillator is disabled.
LATC<1> data output.
PORTC<1> data input.
LATC<2> data output.
PORTC<2> data input.
Timer1 external clock gate input.
CCP2 compare/PWM output. Takes priority over port data.
CCP2 capture input.
LATC<3> data output.
PORTC<3> data input.
Reference output clock.
I
SPI clock output (MSSP module); takes priority over port data.
SPI clock input (MSSP module).
LATC<4> data output.
PORTC<4> data input.
I
SPI data input (MSSP module).
LATC<5> data output.
PORTC<5> data input.
SPI data output (MSSP module).
LATC<6> data output.
PORTC<6> data input.
CAN bus TX.
Asynchronous serial data output (EUSART module); takes priority over port data.
Synchronous serial clock output (EUSART module); user must configure as an
input.
Synchronous serial clock input (EUSART module); user must configure as an
input.
CCP3 compare/PWM output. Takes priority over port data.
CCP3 capture input.
2
2
2
2
C™ clock output (MSSP module); takes priority over port data.
C clock input (MSSP module); input type depends on module setting.
C data output (MSSP module); takes priority over port data.
C data input (MSSP module); input type depends on module setting.
Preliminary
Description
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