PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 223

• Manufacturer Part Number: PIC18F46K80-I/P
• Description: 40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/P

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

FIGURE 14-4:
14.8.2
The Timer1 gate source can be selected from one of
four sources. Source selection is controlled by the
T1GSSx (T1GCON<1:0>) bits (see
TABLE 14-4:
The polarity for each available source is also selectable,
controlled by the T1GPOL bit (T1GCON<6>).
14.8.2.1
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
14.8.2.2
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timer1 gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
 2011 Microchip Technology Inc.
T1GSS<1:0>
00
01
10
11
TMR1GE
T1GPOL
T1GVAL
T1G_IN
Timer1
T1CKI
TIMER1 GATE SOURCE
SELECTION
T1G Pin Gate Operation
Timer2 Match Gate Operation
Timer1 Gate Pin
TMR2 to Match PR2
(TMR2 increments to match PR2)
Comparator 1 Output
(comparator logic high output)
Comparator 2 Output
(comparator logic high output)
TIMER1 GATE SOURCES
TIMER1 GATE COUNT ENABLE MODE
Timer1 Gate Source
N
Table
14-4).
Preliminary
N + 1
PIC18F66K80 FAMILY
Depending on T1GPOL, Timer1 increments differently
when TMR2 matches PR2. When T1GPOL = 1 , Timer1
increments for a single instruction cycle following a
TMR2 match with PR2. When T1GPOL = 0 , Timer1
increments continuously except for the cycle following
the match when the gate signal goes from low-to-high.
14.8.2.3
The output of Comparator 1 can be internally supplied
to the Timer1 gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timer1 will
increment depending on the transitions of the
CMP1OUT (CMSTAT<6>) bit.
14.8.2.4
The output of Comparator 2 can be internally supplied
to the Timer1 gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timer1 will
increment depending on the transitions of the
CMP2OUT (CMSTAT<7>) bit.
N + 2
Comparator 1 Output Gate
Operation
Comparator 2 Output Gate
Operation
N + 3
DS39977C-page 223
N + 4