PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 181

• Manufacturer Part Number: PIC18F46K80-I/P
• Description: 40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/P

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

11.2
PORTA is a seven-bit wide, bidirectional port. The cor-
responding Data Direction and Output Latch registers
are TRISA and LATA.
RA5 and RA<3:0> are multiplexed with analog inputs
for the A/D Converter.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the ANSEL
control bits in the ANCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
 2011 Microchip Technology Inc.
Note:
PORTA, TRISA and
LATA Registers
RA5 and RA<3:0> are configured as
analog inputs on any Reset and are read
as ‘ 0 ’.
Preliminary
PIC18F66K80 FAMILY
OSC2/CLKO/RA6
serve as the external circuit connections for the exter-
nal (primary) oscillator circuit (HS Oscillator modes) or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘ 0 ’. When the device is configured to
use HF-INTOSC, MF-INTOSC or LF-INTOSC as the
default oscillator mode, RA6 and RA7 are automatically
configured as digital I/O; the oscillator and clock
in/clock out functions are disabled.
RA5 has additional functionality for Timer1 and Timer3.
It can be configured as the Timer1 clock input or the
Timer3 external clock gate input.
EXAMPLE 11-1:
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
PORTA
LATA
00h
ANCON1 ; for digital inputs
0BFh
TRISA
; Initialize PORTA by
; clearing output latches
; Alternate method to
; clear output data latches
; Configure A/D
; Value used to initialize
; data direction
; Set RA<7, 5:0> as inputs,
; RA<6> as output
and
INITIALIZING PORTA
OSC1/CLKI/RA7
DS39977C-page 181
normally