PIC18F46K80-I/P Microchip Technology Inc., PIC18F46K80-I/P Datasheet - Page 362

• Manufacturer Part Number: PIC18F46K80-I/P
• Description: 40 PDIP .600IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F46K80-I/P

• A/d Inputs: 11-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 35
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
22.5.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register. If the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
TABLE 22-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS39977C-page 362
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTA1
RCREG1
TXSTA1
BAUDCON1
SPBRGH1
SPBRG1
RCSTA2
RCREG2
TXSTA2
BAUDCON2
SPBRGH2
SPBRG2
PMD0
ODCON
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used for synchronous slave reception.
Name
EUSART SYNCHRONOUS SLAVE
RECEPTION
EUSART1 Receive Register
EUSART1 Baud Rate Generator Register High Byte
EUSART1 Baud Rate Generator Register Low Byte
EUSART2 Receive Register
EUSART2 Baud Rate Generator Register High Byte
EUSART2 Baud Rate Generator Register Low Byte
GIE/GIEH
CCP5MD
ABDOVF
ABDOVF
SSPOD
PSPIF
PSPIE
PSPIP
SPEN
CSRC
SPEN
CSRC
Bit 7
—
—
—
PEIE/GIEL
CCP4MD
CCP5OD
RCIDL
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
RX9
TX9
TX9
—
—
—
CCP3MD
CCP4OD
TMR0IE
RXDTP
RXDTP
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
SREN
TXEN
TXEN
Bit 5
Preliminary
CCP2MD
CCP3OD
TXCKP
TXCKP
INT0IE
CREN
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
SYNC
Bit 4
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
To enable reception, set enable bit, CREN.
Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE
bits (INTCON<7:6>) are set.
CCP1MD
CCP2OD
CTMUIF
CTMUIE
CTMUIP
ADDEN
ADDEN
SENDB
SENDB
BRG16
BRG16
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
UART2MD UART1MD
TMR1GIF
TMR1GIE
TMR1GIP
CCP1OD
TMR0IF
CCP2IE
CCP2IP
CCP2IF
BRGH
BRGH
FERR
FERR
Bit 2
—
—
 2011 Microchip Technology Inc.
TMR2IE
TMR2IP
TMR2IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
OERR
OERR
TRMT
TRMT
U2OD
WUE
WUE
Bit 1
TMR1IE
TMR1IP
TMR1IF
SSPMD
ABDEN
ABDEN
U1OD
RX9D
RX9D
TX9D
TX9D
RBIF
Bit 0
—
—
—